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Unit I
Data Converter
Fundamentals
Op-amp:
Matching of impedance such that the capacitor doesn’t discharge
into the load.
Response dependent on slew rate, sampling will not be
instantaneous at the output.
Major Errors associated with S/H Circuit: Sampling Mode
Acquisition Time: Time taken by the S/H ckt.
To track the analog signal, after the issue of the
sampling command.
Cause: Improper compensation & smaller phase
margin of the op-amp’s closed loop gain.
Worst case: Time required for the o/p to have
transition from zero to Vin(max).
Comprises of Overshoot and Settling Time.
Overshoot: Normalized difference b/w the time
response peak & the steady o/p.
Settling Time: Time required for the response to reach
& stay within a specified tolerance band (usually 2%
or 5%) of its final value.
Major Errors associated with S/H Circuit: Hold Mode
When control signal is removed, the switch turns off &
capacitor holds the sampled value.
Pedestal Error.
Droop.
Aperture Error.
Major Errors associated with S/H Circuit: Hold Mode
Pedestal Error:
Def: Slight reduction in the o/p voltage, after
the removal of the control signal.
Cause: Charge injection onto CH as MOSFET
is turned off.
Droop:
Def:Gradual reduction in the o/p voltage.
Cause: Leakage of current from CH .
Ans: 3.18V
DAC Specifications contd.
Resolution
Def: The smallest change in voltage which can be
produced at the output (or input) of the converter.
No. of Quantization levels corresponds to resolution.
For DAC:
8 bit DAC has 28-1 = 255 equal intervals.
Smallest change in output voltage is (1/255) of full
scale output range. = 0.392 = 1LSB.
It is stated in no. of ways:
8 bit resolution.
A resolution of 0.392 of full scale
A resolution of 1 part of 255.
DAC Specifications contd.
Resolution
For ADC: smallest change in analog input for a one bit
change at the output.
8 bit ADC: is divided into 255 intervals.
Resolution for a 10V input range is 39.22mV (= 10/255 V)
DAC Specifications
O/P voltage of DAC
VOUT = F. VREF
F = D / 2N
Vout = {(110)2/ 23 } x5
=(6/8)x5
=3.75V
Thus , the max analog o/p for this DAC can be,
Vout(max) = (111) 2/ 23 x 5 = 4.375V
DAC Specifications contd.
DAC Specifications contd.
Note
Full Scale Voltage:
VFS = {(2N-1)/ 2N } x VREF
Resolution: 1 LSB = VREF / 2N
More no. of i/p bits results in smaller changes in o/p voltage & thus
yielding better resolution.
N= 12.29 bits = 13
DAC Specifications contd.
Ex. 5) A digitally programmable signal generator
uses a 14 bit DAC with a 10V reference. Find a)
Smallest incremental change at the o/p. b) DAC’s
Full scale value. c) The accuracy.
Ans: a)1LSB = 610µV.
b) VFS = 9.9993V
c) Accuracy = 0.0062%
DAC Specifications contd.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
Cause : Non-linear components within DAC cause increments to
differ from their ideal values.
Def: The difference between the ideal and non-ideal values of the
increments.
DNLn = (Actual increment of transition n) –(Ideal increment height)
Where, n = No. corresponding to digital i/p transition.
DAC Specifications contd.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
DAC Specifications contd.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
Points to remember:
DNL ≤ ± ½LSB. “Monotonic” i.e. the analog o/p does increment as
digital input code is incremented.
IfDNL = ± 1 LSB, then DAC is called as “non– monotonic”.
A 5-bit DAC with 0.75 LSBs DNL actually has resolution of 4-
bit DAC.
So, DAC should exhibit montonicity to work without error.
The overall error of DAC is defined by its worst case DNL.
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
Def: The difference between the data converter o/p values &
the corresponding points on the reference line drawn through
the first & last o/p values.
INLn = (O/p value for i/p code n) – (o/p value on the
reference line)
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
DNL is defined in accordance with the increment height.
i.e. the previous position.
INL defined in accordance with the slop of the curve. i.e.
the transition line.
INL = (Actual o/p voltage) – (Ideal o/p voltage)
Note:
o Using the value of VREF & resolution it is possible to
Also,
DNL
Def: The difference betn the actual code width
of a non-ideal converter & the ideal case.
INL
Def: The difference between the data-
converter code transition points & the ideal
straight line.
• Analog signal sampled at a rate slower than the Nyquist criteria requires.
• the lower frequency signal is an “alias” of the original signal, its frequency
given by falias = factual - fsample
ADC Specifications
Aliasing
Elimination Techniques:
Sampling at higher frequencies.
Filtering the analog signal before sampling &
removing any frequencies that are greater than half
the sampling frequency.
Removes unknown higher order harmonics or noise.
However, adds delay to overall conversion.
= VREF / 2N+1
= 5/ 2N+1
Integrated circuit of
Atmel Diopsis 740
System on Chip
showing memory blocks,
logic and input/output
pads around the
periphery
MIXED SIGNAL LAYOUT ISSUES