FABRICATION

SCHEMATIC CROSS SECTION OF MOSFET

Create N-well
(for PMOS devices) &
Channel Stop Regions

Grow Field &

Gate Oxide

Impurity Implant Into The Substrate.

Thick Around The nMOS And pMOS Active

Regions And Thin Respectively Through Thermal
Oxidation.

Deposit & Pattern

Poly Layer

Implant S, D &
Substrate Contacts

Create Contact
Windows
Deposit & Pattern
Metal Layer

Creation Of n+ And p+ Regions.

Metallization

PHOTOLITHOGRAPHY
IC Is Set Of Patterned Layers Of Doped
Silicon, Polysilicon, Metal And SiO2.
All Areas Are To Be Defined By Proper
Masks.
A Layer Must Be Patterned Before
Another Is Applied On The Chip.
Every Layer Will Undergo Lithography
With Different Mask.

SiO2 layer by thermal oxidation

Si Substrate

Si Substrate

Unpatterned Structure

SiO2

SiO2

Photolithography

Patterned Structure

Chemical or Dry Etch

Hardened Photoresist
Si Substrate

Si Substrate

Si Substrate

Si Substrate

5-200 nm SiO2
layer by thermal
oxidation

Light Sensitive,
Acid Resistant
compound

Hardened Photoresist
SiO2 Window
reaching down to
Si Substrate
Si substrate

Hardened photoresist removed by stripping solvents.

= Photoresist
Si Substrate
UV Light
Glass Mask
Insoluble Photoresist
Si Substrate

Soluble Photoresistv

Obtained Patterned SiO2

feature on the Si Substrate

For High Density Patterns Required In Sub

Micron Devices, E-beam Lithography Is Used
Instead Of Optical Lithography.
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Fabrication of nMOS: Basic steps

Si Substrate

Si Substrate

Thin high
quality Oxide
Layer
(gate oxide)

Deposition of polysilicon
(gate + interconnect medium)

OXIDATION

Si Substrate

Thick Oxide
layer

Si Substrate

(field oxide)

Patterned and etched

SELECTIVE ETCHING FOR DEFINING

ACTIVE AREA ON WHICH MOSFET
WILL BE FABRICATED

polysilicon
oxide

Si Substrate

gate oxide

Si Substrate
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Fabrication of nMOS: Basic steps

Patterned and etched
Insulating oxide

polysilicon

gate oxide

oxide

Si Substrate

n+

n+

Bare Si surface to
form S & D

Patterned and etched

Doping : Diffusion or
ion implantation

Contact windows for

D&S

(high concentration of
impurity atoms)

n+

polysilicon

gate oxide

oxide
n+

n+

n+
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Fabrication of nMOS: Basic steps

Evaporated
Aluminum
n+

n+

Patterned and etched

Metal contacts

n+

n+

By creating another
insulating oxide layer,
cutting contact holes (via),
depositing and patterning
metal, two more layers of
metallic interconnects can
also be added on the top of
this structure.
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CHALLENGES:
Electrical isolation on a single chip containing many
devices is necessary
To prevent undesired conducting paths;
To avoid creation of inversion layers outside the
channels;
To reduce leakage currents.

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DEVICE ISOLATION TECHNIQUES:

I)

ETCHED FIELD OXIDE ISOLATION:

Devices are created in dedicated regions called active
areas.
Each active area is surrounded by thick oxide barrier
called field oxide.
Thick oxide is grown on complete surface of the chip and
then selectively etched to define active areas.
Straight forward method.
Thickness of oxide leads to large oxide steps at the
boundaries of active areas and isolation regions.
May lead to chip failure due to cracking of deposited
layers due to large height difference at the boundaries.11

DEVICE ISOLATION TECHNIQUES:

II Local oxidation of silicon

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LOCOS technique is based on the

principle of selectively growing the
field oxide in certain regions ,
instead of selectively etching away
active areas after oxide growth.
For selective growth of oxide,
active areas are covered with
Silicon nitride.
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DEVICE ISOLATION TECHNIQUES:LOCOS

Thin PAD OXIDE
(stress relief oxide)
Si Substrate

Protects Si surface from stress caused by nitride

during subsequent process steps.

(Patterned and etched)

Si3N4

Si Substrate

(Doping of exposed Si surface with p type impurity)

Si3N4
p+

Si3N4
p+

p+

Isolation Regions
(Channel stop implants)

Si Substrate

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Si3N4

p+

Thick Field Oxide which partially

recesses into Si substrate

Si3N4

p+

p+

Birds beak

Si Substrate

Lateral extension under nitride layer

** Reduces active area

(Patterned and etched)

LOCOS is popular :

THE ACTIVE AREAS

More planar surface topology

p+

p+

Si Substrate

p+

Birds beak encroachment can

be reduced up to some limit
by device scaling

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DEVICE ISOLATION TECHNIQUES:

III) MULTILEVEL INTERCONNECTS & METALLIZATION:
4 to 8 metal layers are used to create interconnections between
the transistors and for routing the power supply, signal lines and
clock lines on the chip surface.
Allows higher integration densities.
Adds to the third dimension.
Electrical connections between the layers are made by vias.
Each via is formed by creating an opening in isolation oxide
before every metallization step and filling it with a special metal
plug (Tungsten).
After creation of via, new metal layer is deposited and
subsequent patterning is done.
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SOME FACTS:
Due to various process steps chip surface is highly
nonplanar.
It may inhibit local thinning and discontinuities at uneven
surface edges.
Deposition of multiple metal interconnect lines is not
desirable on such irregular topography.
They will lead to hills and valleys on the chip surface.
Hence surface is usually planarised before every new metal
deposition step.
For this, a fairly thick SiO2 layer is grown on the wafer
surface to cover all existing surface nonuniformities.
Its surface is then planarised by any one of:
Glass reflow (heat treatment),
Etch back,
Chemical mechanical polishing (CMP).
CMP: Actual polishing of wafer surface using abrasive silica
slurry.
Adopted in recent years.

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EXERCISE:
*Epitaxial layer
** Difference between ion
implantation and diffusion processes
of doping.
*** Design masks for all patterning
and etching steps in the fabrication
of nMOS transistor for positive and
negative photoresist material.
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