PLA Testing

Under guidance of,

Prof. P. P. Gundewar

By,
Kalpak Shahan

14.1 Introduction
PLA consist of
Input decoder
AND Array
OR Array

PLA implements Two logic levels

NAND-NAND
NOR-NOR

For simplicity we consider an

AND+OR circuit

Introduction
PLA described by - Matrix P = ( A,O )
Where A m x n (representing AND
Array)
O m x k (representing OR Array)
m, n, k are inputs product terms and outputs

this Matrix is called as PLAs

personality

A PLA structure with 1 bit

decoders

m x n matrix AND array

m x k matrix OR array
Intersection of
bit or output
line crosspoint
At each
crosspoint a
transistor exists
And if
connection isnt
wanted disable
transistor

Example
For an AND array
1 - Xi , 0 Xi
x - Dont care
(connection absent)

For OR array
1 - connection present
0 - connection absent

PLA shown
implements function
f1= X1 + X3X4 + X2X3
f1= X3X4 + X1X2X3X4 +
X2X3 +
X1X2X3X4

PLA Testing problems

PLA testing an important issue.
Though PLAs offer many advantages,
they also present new testing
problems.
Fault Models

Shrinkage fault
Growth fault
Appearance fault
Disappearance fault

Fault Models
Most common stuck at Fault
s-a-1 or s-a-0 can occur at any wire within input
output lines bit lines and product lines.

Stuck-at faults alone cannot model all

physical defects in PLAs
New class of fault named crosspoint faults
can occur in PLA
crosspoint fault is either an extra or a
missing connection at a crosspoint in the
AND or OR array of a PLA

Sr.
No.

Fault

Shrinkage

Growth

Appearance

Disappearan
ce

Extra
Missing
connection connection
between
between
Bit line and
product line

Cause

Includes 1
additional input
Bit line and
product line

Product line
and output
line

becomes
independent of
additional input
Corresponding
implicant appears
in output

Product line
and output
line

Corresponding
implicant
disappears in
output

Missing crosspoint equivalent to stuck faults

Extra connections cannot be modeled by
stuck faults

are (2n + k)m possible single

there

crosspoint faults and 1 different single

and multiple crosspoint faults.
Multiple faults are common in PLAs.
Faults in PLA
Multiple stuck faults
Multiple crosspoint faults
Combinations of these faults

PLAs can be modeled as OR or AND

bridging faults because either a "high" or
"low" voltage will dominate.

14.2.2 Problems with Traditional Test

Generation Methods
PLA corresponds to two-level sum-of-product
circuit with input inverter
nMOS technology it is often implemented by two
levels of NOR-NOR gates with output inverters
One way to generate tests for a PLA is first to
convert the PLA into a two-level gate circuit and
then to find tests for stuck faults in the
"equivalent" gate circuit.
Many traditional algorithms exist and these
methods share two serious problems.
two-level circuit is logically equivalent to the PLA,
as far as fault behaviour is concerned, they are not
equivalent.

Problems with Traditional Test

Generation Methods
extra crosspoint fault in the AND array,
cannot be modeled as a stuck fault in the
gate circuit.
high fault coverage is not guaranteed
traditional test generation algorithms are
not always effective for PLAs because PLAs
have high fanin ,fanout and redundancy.
Although exhaustive testing is not affected
by these factors, it becomes less applicable
as the size of the PLA increases.

 Thank you