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Coprocessor
Operation performed :
They are Unable to fetch the code from the memory so they work under the
control of main processor .
Architecture of 8087
Intel 8087
Numeric Processor.
Packed in 40 pin ceramic DIP package.
Available in 5 MHz, 8MHz, 10MHz versions compatible with 8086,
8088, 80186, 80188.
It adds 68 new instruction to the instruction set of 8086.
How it works :
The 8087 instruction may lie interleaved in the 8086 program, but it
is the task of 8086 to identify the 8087 instructions from the program,
send it to 8087 for further execution & after the completion of
execution cycle the result may be referred back to CPU.
Operation of 8087 does not require any software support from the
system software or operating system.
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Architecture of 8087
Control unit
Numeric Execution unit
Control Unit :
Function :
It interface the coprocessor to the microprocessor
system data bus.
Monitors the instruction stream.
If the instruction is an ESCape (coprocessor)
instruction, the coprocessor executes it; if not the
microprocessor executes it.
It receives , decodes instructions, read and write
memory operands and executes the 8087 instruction.
8
Programmable shifter :
Responsible for shifting the operands during the execution of
instruction like FMUL and FDIV.
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10
11
1) B busy bit
4) ES error summary
5) PE precision error
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6) UE Underflow Error
7) OE Overflow Error
8) ZE Zero Error
Indicates the divisor was zero while the dividend is a noninfinity or non zero number.
9) DE Denormalized error
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Control register
1)
IC Infinity Control
2)
RC Rounding Control
00
01
10
11
15
3) PC Precision Control
00
01
10
11
4) Exception Masks
5) Zero Divide
6) Denormalized Operand
Tag Register
The tag register indicates the contents of
each location in the coprocessor stack.
The tag indicates whether a register is valid;
zero; invalid or infinity; or empty.
Figure illustrates the tag register and
the status indicated by each tag.
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19
20
21
22
1)
AD0 - AD15 :
2) A19/S6 A16/S3 :
3) BHE / S7 :
4) Qs1 , Qs0 :
Qs1 , Qs0 are queue status input signals.
These enable 8087 to keep track of the instruction prefetch
queue status of the CPU, to maintain synchronism with it.
Qs1
0
0
1
1
Qs0
0
1
0
1
Queue Status
No operation.
First byte of opcode from queue
Empty Queue
Subsequent byte from queue.
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5) INT
6) BUSY
7) READY
8) RESET
9) CLK
10) VCC
A +5V supply
11) GND
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S1
S0
Queue status
unused
Unused
Memory read
Memory write
passive
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13) RQ / GT0
The request / grant pin is used to gain control of the bus from
the host (8086/ 8088) for operand transfer.
An active low pulse of one clock duration is generated by
8087 for the host to inform it that it wants to gain control of
the local bus either for itself or for other coprocessor
connected to RQ/ GT1 pin of 8087.
The 8087 waits for the grant pulse from the host.
When it is received, it either initiates a bus cycle if the
request is for itself or else, it passes the grant pulse to
RG/GT1, if the request is for the other coprocessor.
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14) RQ / GT1
Bidirectional pin
Used by other bus masters to convey their need of the local
bus access to 8087.
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The busy pin of 8087 is connected with the TEST pin of the
CPU.
In 8086/8088 the QS0 &QS1 lines may be directly connected to
the corresponding pins.
8259 - Programmable interrupt controller
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In case of 8086 / 8088 based system the RQ/ GT0 of 8087 may be
connected to RQ / GT1 of 8086/ 8088.
The clock pin of 8087 may be connected with the CPU 8086/ 8088
clock input.
The interrupt output of 8087 is routed to 8086/8088 via a
programmable interrupt controller.
The pins AD0 AD15 , RESET , A19 /S6 - A16 /S3 , BHE / S7 are
connected to the corresponding pin of 8086/8088.
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33
1.
2.
3.
4.
5.
6.
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1)
;
;
ST (6)
2) FIST/FISTP
The instruction work in exact similar manner as FST/
FSTP except the fact that the operand are integer
operand.
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Arithmetic Instructions
1.
2.
3.
4.
5.
6.
FADD
FSUB
MUL
FDIV
FSQRT
FABS
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FSQRT
Finds the square root of the top of the
stack and leaves the resultant square
root at the top of the stack.
an invalid error occurs for the square
root of a negative number
FSCALE
Adds the contents of ST(1) (interpreted as
an integer) to the exponent at the top of the
stack.
FSCALE multiplies or divides rapidly by
powers of two.
value in ST(1) must be between 215 and 2+15
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FPREM/FPREM1
Performs modulo division of ST by ST(1).
The resultant remainder is found in the top
of the stack and has the same sign as the
original dividend.
a modulo division results in a remainder
without a quotient
Arithmetic-Related Operations
Decomposes the number at the top of the
stack into separate parts representing value
of the unbiased exponent and significand.
The extracted significand is found at the top
of the stack and the unbiased exponent at
ST(1).
often used to convert a floating-point to a form
that can be printed as a mixed number
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FRNDINT
Rounds the top of the stack to an integer.
FABS
Changes the sign of the top of the stack to
positive.
FCHS
Changes the sign from positive to negative
or negative to positive.
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FTST
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Transcendental Instructions
The operand usually are ST(0) and ST(1) or only ST(0)
FPTAN :
Instruction calculates the tangent of an angle O, where O, must
FPATAN :
Instruction calculates the inverse tangent
The result is stored on the top of the stack.
The content of ST and ST(1) should follow the inequality.
0<=ST(1) < ST< infinity
F2XMI :
Instruction calculates the expression (2x - 1)
Value of x is stored at the top of the stack.
Result is stored back at the top of the stack.
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FLY2X
It calculate ST(1) * Log2 ( ST)
Result is stored back at the top of stack.
ST must be in the range of 0 to +infinity.
ST(1) must be in the range of -infinity to +infinity.
FLY2XP1
It calculate ST(1) * log2[ (ST)+1 ]
Result is stored back on the stack top.
|ST| must lie between 0 and (1- 21/2 /2).
Value of ST(1) must lie between infinity and + infinity
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Comparison Instruction
All the comparison instructions compare the operands and modify the
condition code flags
Comparison
C3
C0
Not Comparable
1
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1.
FCOM
2. FIST
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2. FLDPI
Load pi(3.14) to stack top
3. FLDLG2
Load the constant Log10 2 to the stack pointer.
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I. FINIT
II. FENI
III. FDISI
IV. FLDCW
V. FSTSW
VI. FCLEX
VII. FFREE
VIII. FNOP
IX. FWAIT
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