VLSI-DSP Based Embedded

System : An Overview

Prof. Swapna Banerjee

Department of Electronics &
ECE
Indian Institute of Technology,
Kharagpur - 721302

A Brief History
Digital Signal Processing was born in the 1960s. The (re)discovery of the
Fast Fourier Transform, marked the birth.
Special purpose DSP chips also saw their birth in the late 1970s. This class
of chips uses special arithmetic structures and arrays-have driven much of the
work in VLSI Research Group.
In the 1990s, a merger of two architectures into programmable DSP chips
with special hardware functions. An example TMS320C8x generation contain
several DSP cores with a master RISC controller and an IEEE standard floating
point ALU.
Field Programmable Gate Arrays (FPGAs), came onto the market in the
1980s. Devices are ubiquitous, with RAM based designs. The densities of
FPGAs have now reached the point where they are serious contenders for
implementing small DSP arrays.
The advantage, of this programmable approach, is a very fast design cycle
with the ability to correct errors and update features without a change of
hardware; thus the sacrifice in inefficiency is acceptable.

The state-of-the-art at 2010 allow 2 orders of magnitude increase

in DRAM and SRAM bits in the following Table.
Driver
Year of first DRAM shipment

1995

1998

2001

2004

2007

2010

Feature Size (m)

.35

.25

.18

.13

.10

.07

DRAM bits/Chip

64M

256M

1G

4G

18G

64G

SRAM (cache) Bits/cm2

2M

6M

20M

50M

100M 300M

L(P)

Logic Transistors/cm2 (packed)

4M

7M

13M

25M

50M

90M

L(P)

On-chip clock (MHz) (high perf. DSP)

400

600

800

1100

1500

1900

DSP

Wiring Levels (Logic)

4-5

5-6

6-7

7-8

Power Supply (Desktop)

3.3

2.5

1.8

1.5

1.2

0.9

Power Supply (Battery)

2.5

1.8-2.5

0.9-1.8

0.9

0.9

0.9

Maximum Power W (high perf. w.

heat-sink)

80

100

120

140

160

180

Design issues associated with the technology include:

Algorithm design
Architecture design
Implementation technology
Verification and test
Library circuit design
Arithmetic implementation

The combination of constantly evolving DSP algorithm with

DSPP hardware have formed the basis for an exponential
growth in DSP applications.
Table : The following table summarizes some of the key features
of the DSPPs
TMS32060

DSP96002

TMS32080

ADSP21060

DIVIDE

45ns

233ns

125ns

150ns

PRECISION

32bits

32bits

32bits

32bits

RAM/ROM

1Mbit

8Kbytes

50Kbytes

4Mbytes

33.3ns

25ns

25ns

I CYCLE TIME 5ns

Figure : Heterogeneity in the top-down design flow of complex systems

Subsystem
audio processing
digital image processing
image/ video resampling
user interface
communication protocols
digital control
image understanding
scalable descriptions

Model of Computation
1-D dataflow
2-D dataflow
m-D multirate dataflow
synchronous/ reactive
finite-state machine
dataflow
knowledge-based control
process networks

Table : Models of computation for describing the signal processing,

communications, and control aspects of image and video processing systems.

Figure . Typical structure of a large system

Figure . A heterogeneous hardware and software platform.

I/P
Search
Window

DSP

FPGA
DSP + FPGA

Video Stream
External Video
Frame Buffers
Reconstructed
Frame

Figure: Macroblock-based pipeline processing

DaVinci technology integrated portfolio of DSP-based processors,

software, tools, and support for developing a broad spectrum of
optimized digital video end equipments.
DaVinci processors :
- Digital cameras
- Video telephones
- IP set-top box
- Automotive infotainment

- Video security
- Portable media players
- Medical imaging
- Networked video for emerging applications.

Inter-chip communication is critical in the implementation model.

Figure : Architecture B significantly increases DSP/FPGA/memory interactions.

Ptolemy uses object-oriented software principles to achieve the

following goals:
Agility: Support distinct computational models, so that each
subsystem can be simulated and prototyped in a manner that is
appropriate and natural to that subsystem.
Heterogeneity: Allow distinct computational models to coexist
seamlessly for the purpose of studying interactions among
subsystems.
Extensibility: Support seamless integration of new
computational models and allow them to interoperate with
existing models with no changes to Ptolemy or to existing
models.
Friendliness: Use a modern graphical interface with a
hierarchical block-diagram style of representation.

Typical SOC Architecture will have:

A processor core
One or more caches
On chip bus hierarchy
On chip memory
A large number of peripheral cores (they provide
application specific functionality such as multimedia
and communication processing)

A designer must have a method for finding a feasible set of

parameter values, referred to as a configuration of the SOC
that meets the specification requirements.

The System
Patient

You may say I'm a dreamer

But I'm not the only one
I hope someday you'll join us
And the world will be as one

Adaptive
Control

Sensor
Pre-processing
Unit

Expert
System

Data Bank

ADC
Signal Proc
Unit

COMPUTER

Image
Processing
Unit

Comm.
Interface

Sensors
Resistive sensors, Inductive/ Capacitive Sensors
Quasi-digital sensors:
Gives outputs with variable frequency, pulse-rate
or pulse duration that are easily converted to digital signals.
Piezoelectric sensors
Thermistors
Fiber-Optic Temperature sensor
Laser
Photo conductive cells
Photo junction sensors

Domain of VLSI
Diagnostic products
Therapeutic products
Analytical Instruments
Monitoring Instruments
Rehabilitative Devices
Processing Instrument

VLSIs

Objectives

Design Domain

Low Power System

Real-time Processing
High Precision Design
Algorithmic Applicability
Analog Front-end Design
Digital Signal Processing units viz. DFT, DCT, DHT and DST

Implementation Platform

Xilinx FPGA
Synopsys and Cadence (ASIC Platform)

VLSI based Doppler

ultrasonography system

Spectrogram

Image
Contour
Detection
Inertial Snake

Feature
Extraction
BP Neural Network

Contour Motion
Detection

Flow
Diagnosis

Probability
measure
Bayesian Probability

Probability
Measurement
Bayesian Probability
Arterial
Condition
(probabilistic)

Final
Inference

Arterial Condition
detection

Doppler Ultrasonography System

Analog
Frontal
End

A/D Conversion
Sampling
Frequency 32KHz

PCI Bus
Interface
8-bit data to PC

PZT Transducer
f0= 8MHz

128 Point FFT

CORDIC Processors
(16-bit operation
8-bit o/p)

f0f
Knowledge
Base

8-bit data
Display
(spectrogram)

Low-cost Colour Doppler Ultrasonograp

Different Parameters in the

Systolic peak (S)
spectrogram
SB

Period
Systolic Window (SW)

SB: Spectral Broadening

Diastolic trough (D)

Structure of the Knowledge Base system

Age and
Region based
Grouping

Input
Spectrograms

Feature
Extraction

No

I = N?

Yes

Yes

Known
Pattern?

ANN
based
classifier

No
Add to
Database

Upgrade
Classifier

Train

Store
Weight
Matrix

Inference

BPNN Structure
A
B

i-nodes

k-nodes
j-nodes

S/D
P

Distal Stenosis
Proximal Stenosis

SW
SBI
CK
C

Normal

Vasodilatation
Wij

Wjk

Ischemic

Arterial Distribution in Human Body

Right External Carotid Artery

Left External Carotid Artery

Left Common Carotid Artery

Heart

Aorta

Radial
Ulnas

Common Femoral
Popletial

Brachial

Posterior Tibial

Anterior Tibial

Knowledge-Base Development

Spectrogram recognition
using BPNN

The main components of DSP/DIP systems

Spectral analysis of time varying signals (ECG, EEG, EMG,

EGG, Doppler ultrasonography signal etc.)

Discrete Fourier Transform (DFT) and Discrete Hartley

Transform (DHT)

Archiving the digitized data in compressed format

Discrete Cosine Transform (DCT) and Discrete Sine

Transform (DST)

Also used for reconstruction of MRI image and

delineation of the ECG signal into its component waves

Pattern recognition for bone fractures, tumors and

detection of abnormal cell nuclei

Hough Transform (HT)

Unified architecture of DXT

(DFT/DCT/DHT/DST)

or a real sample sequence f(n), where n {0, 1, , N-1} DXT can be defined as
N 1

DFT: F(k) = f (n)[cos(2 / N )kn j sin(2 / N )kn] = Fx(k) + j Fy(k)

n 0

DHT:
=

N 1

H(k)
f (n)[cos(2 / N )kn sin(2 / N )kn]

(2)

(3)

(4)

n0

N 1

DCT: C(k) = f (n) cos[k (2n 1) / 2 N ]

n 0

N 1

DST: Z(k) = f (n 1) sin[k (2n 1) / 2 N ]

n 0

Reformulation in terms of CORDIC rotation

DFT

F (k )
x

DHT

F ( k ) f ( n)

0 Rot (m )

N 1

n 0

N 1

H (k )

H ( N k ) f ( n)

C (k )

C ( N k ) [ r ( n)

n 0

f (n) Rot (m )

DCT

DCT

S(N k)

N 1
n0

N 1

S ( k ) [ r ( n)
n 0

0 Rot (m )]Rot (k)

0 Rot (m )]Rot ( k )

Reformulation in terms of CORDIC rotation

(contd.)
k = 0, 1, ....., N 1
m = kn modulo N = <kn>N

= 2/N,
= /4
for n = 0, 1, ....., (N 1)/2

r(n) = f(2n)

= f(2N 2n 1) for n = (N + 1)/2, ....., (N 1)

The Unified Equation for DXT

Y ( k )
x

Y (k ) [ h ( n)
N 1

n 0

h (n) Rot (m )]Rot (k)

y

Arrangement of CORDIC unit for DXT

Basic CORDIC Matrix

sin
cos
sin cos Rot ( )

Rot ( .... ) Rot Rot .....Rot

1

fy(n1)

fy(n)

fy(1)

fx(n1)

fx(n)

fx(1)

Ux(N1)

Cm

Cm

1
PC

Cm

2
PC

(N1)

Uy(N1)
PC

Processing Element
xi
xi1

Rx

Ry

xf

x i/

yf

y i/

Mode
Control
Unit

yi1

Rz

Cm

PC

PCi

Clock

DXT Architecture
FIFO Bank
D
A
T
A

D
A
T
A

D
A
T
A

(N 1)/2

f0
Switch and control structure
0

M
U
X

(N 1)/2

(N 1)/2

[Y(1) Y(N 1)]

1
M
U
X

Select

Y(N 1)/2

Core and critical path of the DXT Chip

PCI Based Ultrasonography System

HARDWARE
MEMORY
BANK1

FPGA5

MEMORY
BANK2

FPGA 1
FPGA6

ADDER

FPGA 2
FPGA 3

AMPLITUDE
EXTRACTOR

SCAN
CONVERSION

NOISE
CLEANING

FPGA 4
POWER CONTROL OF
LOSSY/
TRANSMIT
LOSSLESS
BEAMFORMER

BRIDGE

LOSSLESS

MOVIE /
STATIC

USB
APPLICATION
PROGRAM

CONTROL SIGNAL
GENERATION FOR
HARDWARE

FINE NOISE
CLEANING

PC NORTH
BRIDGE

DISPLAY
(PC MONITOR)
STORAGE
(HARD DISK)

PC

Software

DELAY VALUE
GENERATOR
DELAY
MEMORY

APODIZATION
UNIT
FOR CHANNEL: 1
WEIGHTAGE

FOR CHANNEL: 16
DELAY
MEMORY

FPGA

ADDER

CONTOUR
DETECTION

DRIVER

TGC GAIN
CONTROL

LOSSY /

DATA
COMBINER

PCI

MOVIE/
STATIC

COMPRESSION
(DWT+CODING)

WEIGHTAGE

1/2/3/4

COHERENTLY
ADDED
OUTPUT

VLSI based Doppler

ultrasonography system

Spectrogram

Image
Contour
Detection
Inertial Snake

Feature
Extraction
BP Neural Network

Contour Motion
Detection

Flow
Diagnosis

Probability
measure
Bayesian Probability

Probability
Measurement
Bayesian Probability
Arterial
Condition
(probabilistic)

Final
Inference

Arterial Condition
detection

Basic CT system
CT collects projections.

Radon Transform image x,y y px dydx Projections(p, )

Projected X-ray data.

Problems of FBP
Polar domain computation.
Need for conversion from Raster Scan Grid to Polar Grid.
Data interpolation.

Solution Slope-Intercept ( p- ) domain Radon Transform :

Slope -Intercept Radon Transform (Beylkin, 1987)

Fast Radon Transform (FRT)

(Kelly- Madisetti, 1993).

New FRT (Mitra- Banerjee, 2004).

Improvement

p- Radon Transform

Image , u x, y

u x, y y px dydx

Line integrals along various angles and intercepts in an image

plane.
Mathematical Basis of the Image Reconstruction from Projections
(e.g. X-ray CT, MRI ).

A straight line in an
image space

Line function ( Line Sampler ) at

8o

Projection data

p- Radon Transform in Frequency Domain

RT : R u m, l F 1 U L k LP k
IRT : u m, l F 1 WP k PL k
UL(k) frequency domain image function
LP(k) frequency domain line function
WP(k) frequency domain filtered Radon transform.
Composition of LP(k) and PL(k) are different.

Problems of the Frequency Domain Technology

(i) Line function aliasing for angle, > tan-1(r) ,
r Image aspect ratio,
for a Square Image r =1, hence max() < 45o.

Line function (Line Sampler)

at 8o

Line function at 60.95o showing

aliasing effect.

Our solution
y

450

450

An Image space divided

into two angular parts

Below 450

Above 450

Flow Diagram
i/p Image

FRT below 45o

FRT above 45o

FRT below 45o

FRT above 45o

Reconstructed
Image

New FRT Algorithm.

FPGA Module for image processing

A module with Virtex-II FPGA & 256 Mb of external RAM.

Result
Original Image

below 45o

Complete Reconstruction

above 45o

Back-Projection
Reconstruction

FRT based Image Reconstruction for CT

CLK
imaging
S in o g ram
b e lo w 4 5

12

FFT

16

16
RAM 1

F ilte r

PU1

V e cto r-M a trix

M u ltip lie r

cos

s in

12

16
RAM 1

IF F T

RAM 1

12
+

LS (k )
PU2
12

S in o g ram
ab o ve 4 5

FFT

RAM 2

F ilte r

cos

s in

V e cto r-M a trix

M u ltip lie r

O u tp u t
im a g e

RAM 2

IF F T

RAM 2

C o re P ro cessing U nit
C o n tr o l
U nit

RAM 1

RECONSTRUCTED
3-D IMAGE

Glucose Monitoring and Drug Delivery System

Porous Silicon
MEMS Sensor

Laser Source
With optics

Signal
Processing
Circuit

LUT based
Controller

Attenuators
Laser

Signal Detector

PZT Crystal

Joule-meter

Digital
Oscilloscope

Infusion
pump

0.8
0.7

PA SIGNAL IN mv

0.6
0.5
0.4
0.3
0.2
0.1
0

10

15

20
TIME IN MINUTE

25

30

35

40

VARIATION OF PA SIGNAL OF A SUBJECT WITH

TIME AFTER DRINKING GLUCOSE WATER

ABSORPTION SPECTRUM OF TISSUE & BLOOD

RELATIVE PA CHANGE(%)

PA SIGNAL VS GLUCOSE CONCENTRATION

GLUCOSE CONCENTRATION(%)
RELATIVE PA CHANGE OF GLUCOSE SOLUTION WITH DIFFERENT CONCENTRATION

VARIATION OF INSULIN WITH

GLUCOSE
TIME(min) GUCOSE(mg/dl)

INSULIN(Uu/ml)

92

11

350

26

287

130

251

85

240

51

10

216

49

12

211

45

14

205

41

16

196

35

MRI
Signal Localization
Slice selection
Fourier transform

Spatial Information Encoding

Freq Encoding
Phase Encoding
Affine Transform

Image Guided Surgery

a priori

Imagery
sub-system
MRI Skin
Segmentation

Subject
Laser
sub-system
Laser
Scanner
Laser
Data/MRI
Registration

MRI Internal
structure
segmentation

Tracking
Sub-system
Head
Tracking

Instrument
Tracking

Head
Tracking
Verification

Registration
Verification

Laser/Flashpoint
Calibration

Visualization
sub-system

MR Imaging Process viewed as two mathematical

transformations
Transform I
Spin Processing

Data
Space

object

image

Data
processing
Transform II

e-ear

Seeing through the sand

Telemedicine System

The Destination

May
May
May
May

there
there
there
there

be
be
be
be

peace
peace
peace
peace

in heaven.
in the sky.
on earth.
in the water

Design of VLSI based biomedical

instruments with adaptive monitoring
and drug-delivery system