Introduction to 8086

Microprocessor

Features of 8086
It

is 16 bit processor. So that it has 16 bit ALU,

16 bit registers and internal data bus and 16
bit external data bus. It make s faster
processing.
It has three version based on the frequency of
operation:

8086 -> 5MHz

8086-2 ->8MHz
8086-1 ->10 MHz

Features of 8086 (cont..)

8086

has 20 bit address lines to access

memory. Hence it can access
2^20 = 1 MB memory location.
8086 has 16-bit address lines to access I/O
devices, hence it can access
2^16 = 64K I/O location

Features of 8086 (cont..)

Pipelining:-8086

uses two stage of

pipelining. First is Fetch Stage and the
second is Execute Stage.

Fetch stage that prefetch upto 6 bytes of

instructions stores them in the queue.
Execute stage that executes these instructions.

Pipelining

improves the performance of the

processor so that operation is faster.

Features of 8086 (cont..)

Operates

in two modes:-8086 operates in two

modes:

Minimum Mode: A system with only one

microprocessor.
Maximum Mode:-A system with multiprocessor.

8086

uses memory banks

The 8086 uses a memory banking system. It means entire

data is not stored sequentially in a single memory of 1 MB
but memory is divided into two banks of 512KB.

Features of 8086 (cont..)

Interrupts

8086 has 256 vectored interrupts.

Multiplication

And Division

8086 has a powerful instruction set. So that it

supports Multiply and Divide operation.

Architecture of 8086
The

architecture of 8086 includes

Arithmetic Logic Unit (ALU)

Flags
General registers
Instruction byte queue
Segment registers

EU & BIU

The 8086 CPU logic has been partitioned into two

functional units namely
Bus Interface Unit (BIU)
Execution Unit (EU)

The major reason for this separation is to increase the

processing speed of the processor
The BIU has to interact with memory and input and
output devices in fetching the instructions and data
required by the EU
EU is responsible for executing the instructions of the
programs and to carry out the required processing

EU & BIU

Architecture Diagram

Execution Unit
The

Execution Unit (EU) has

Control unit
Instruction decoder
Arithmetic and Logical Unit (ALU)
General registers
Flag register
Pointers
Index registers

Execution Unit
Control

unit is responsible for the coordination of all other units of the processor
ALU performs various arithmetic and logical
operations over the data
The
instruction decoder translates the
instructions fetched from the memory into a
series of actions that are carried out by the
EU

Execution Unit - Registers

The EU has eight general purpose registers labeled

AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually for temporary
storage of 8-bit data.
The AL register is also called the accumulator.
Certain pairs of these general purpose registers can
be used together to store 16-bit data.
The valid register pairs are AH and AL, BH and BL, CH
and CL and DH and DL.
These register pairs is referred to the AX, BX, CX, and
DX resp.

Execution Unit - Registers

1. AX Register: For 16-bit operations, AX is called the

accumulator register that stores operands for
arithmetic operations.
2. BX Register: This register is mainly used as a
base register. It holds the starting base location of a
memory region within a data segment.
3. CX Register: It is defined as a counter. It is
primarily used in loop instruction to store loop counter.
4. DX Register: DX register is used to contain I/O
port address for I/O instruction.

Execution Unit - Registers

Execution Unit - Flags

Execution Unit - Flags

Overflow Flag (OF) - set if the result is too large

positive number, or is too small negative number to
fit into destination operand
Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If
cleared then the index registers will be autoincremented
Interrupt-enable Flag (IF) - setting this bit enables
maskable interrupts
Single-step Flag (TF) - if set then single-step
interrupt will occur after the next instruction

Execution Unit - Flags

Sign Flag (SF) - set if the most significant bit of the

result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry
from or borrow to bits 0-3 in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits)
in the low-order byte of the result is even.
Carry Flag (CF) - set if there was a carry from or
borrow to the most significant bit during last result
calculation

Execution Unit - Flags

Execution Unit - Pointers

Stack Pointer (SP) is a 16-bit register pointing to

program stack
Base Pointer (BP) is a 16-bit register pointing to data
in stack segment. BP register is usually used for
based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect
addressing, as well as a source data addresses in
string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used
for indexed, based indexed and register indirect
addressing, as well as a destination data addresses
in string manipulation instructions.

Execution Unit - Pointers

Bus Interface Unit

The

BIU has

Instruction Queue
Segment registers
Instruction pointer

BIU Instruction Queue

To increase the execution speed, BIU fetches as many as

six instruction bytes ahead to time from memory.
The prefetched instruction bytes are held for the EU in a
first in first out group of registers called a instruction
queue.
When the EU is ready for its next instruction, it simply reads
the instruction from this instruction queue.
This is much faster than sending out an address to the
system memory and to send back the next instruction byte.
Fetching the next instruction while the current instruction
executes is called pipelining.

BIU Instruction Byte Queue

Execution and decoding of certain instructions do

not require the use of buses
While such instructions are executed, the BIU
fetches up to six instruction bytes for the following
instructions (the subsequent instructions)
The BIU store these prefetched bytes in a first-infirst out register by name instruction byte queue
When the EU is ready for its next instruction, it
simply reads the instruction byte(s) for the
instruction from the queue in BIU

Segment Registers
The

memory of 8086 is divided into 4 segments

namely
Code segment (program memory)
Data segment (data memory)
Stack memory (stack segment)
Extra memory (extra segment)
These segment registers are used to hold the upper 16
bits of the starting address for each of the segments.
The part of a segment starting address stored in a
segment register is often called the segment base.

Instruction Pointer (IP)

The

instruction pointer (IP) holds the 16-bit

address of the next code byte within this code
segment.