Chapter7

ComplementaryMOS(CMOS)Logic
Design
MicroelectronicCircuitDesign
RichardC.Jaeger
TravisN.Blalock

Jaeger/Blaloc

MicroelectronicCircu

Chap71

ChapterGoals

IntroduceCMOSlogicconcepts
ExplorethevoltagetransfercharacteristicsCMOSinverters
Learntodesignbasicandcomplexlogicgates
DiscussstaticanddynamicpowerinCMOSlogic
PresentexpressionsfordynamicperformanceofCMOSlogic
devices
PresentnoisemarginsforCMOSlogic
IntroducedynamiclogicanddominoCMOSlogictechniques
Introducedesigntechniquesforcascadebuffers
ExplorelayoutofCMOSlogicgates
Discusstheconceptoflatchup

Jaeger/Blaloc

MicroelectronicCircu

Chap72

CMOSInverterTechnology
ComplementaryMOS,orCMOS,needsboth
PMOSandNMOSdevicesfortheirlogicgatesto
berealized
TheconceptofCMOSwasintroducedin1963by
WanlassandSah,butitdidnotbecomecommon
untilthe1980sasNMOSmicroprocessorswere
dissipatingasmuchas50Wandalternative
designtechniquewasneeded
CMOSstilldominatesdigitalICdesigntoday
Jaeger/Blaloc

MicroelectronicCircu

Chap73

CMOSInverterTechnology
TheCMOSinverterconsistsofaPMOSstackedontopon
aNMOS,buttheyneedtobefabricatedonthesamewafer
Toaccomplishthis,thetechniqueofnwellimplantation
isneededasshowninthefigurewhichshowsthecross
sectionofaCMOSinverter

Jaeger/Blaloc

MicroelectronicCircu

Chap74

CMOSInverter

(a) CircuitschematicforaCMOSinverter
(b) Simplifiedoperationmodelwithahighinputapplied
(c) Simplifiedoperationmodelwithalowinputapplied

Jaeger/Blaloc

MicroelectronicCircu

Chap75

CMOSInverterOperation
WhenvIispulledhigh(VDD),thePMOSinverter
isturnedoff,whiletheNMOSisturnedonpulling
theoutputdowntoVSS
WhenvIispulledlow(VSS),theNMOSinverteris
turnedoff,whilethePMOSisturnedonpulling
theoutputuptoVDD

Jaeger/Blaloc

MicroelectronicCircu

Chap76

CMOSInverterLayout

Jaeger/Blaloc

MicroelectronicCircu

Twomethodsof
layingoutaCMOS
inverterareshown
ThePMOStransistors
liewithinthenwell,
whereastheNMOS
transistorslieinthep
substrate
Polysiliconisusedto
formcommongate
connections,andmetal
isusedtotiethetwo
drainstogether

Chap77

StaticCharacteristicsoftheCMOS
Inverter
Thefigureshowsthe
twomodesofstatic
operationwiththe
circuitandsimplified
models
NoticethatVH=5V
andVL=0V,andthat
ID=0Awhichmeans
thatthereisnostatic
powerdissipation
Jaeger/Blaloc

MicroelectronicCircu

Chap78

CMOSVoltageTransferCharacteristics
TheVTCshownisfora
CMOSinverterthatis
symmetrical(KP=KN)
Region1:vO=VH
vI<VTN
Region2:|vDS| |vGS VTP|
Region4:vDS vGS VTN
Region5:vO=VL
vI>VDD|VTP|

Jaeger/Blaloc

MicroelectronicCircu

Chap79

CMOSVoltageTransferCharacteristics
Thesimulation
resultshowsthe
varyingVTCof
theinverteras
VDDischanged
Theminimum
voltagesupply
foracertainMOS
technologyis
2VTln(2)
Jaeger/Blaloc

MicroelectronicCircu

Chap710

CMOSVoltageTransferCharacteristics

Jaeger/Blaloc

MicroelectronicCircu

Thesimulation
resultshowsthe
varyingVTCofthe
inverterasKN/KP=
KRischanged

ForKR>1the
NMOScurrent
driveisgreaterand
itforcesvI<VDD/2

ForKR<1the
PMOScurrentdrive
isgreaterandit
forcesvI>VDD/2

Chap711

NoiseMarginsfortheCMOSInverter
Noisemargins
aredefinedby
theregions
showninthe
givenfigure

Jaeger/Blaloc

MicroelectronicCircu

Chap712

NoiseMarginsfortheCMOSInverter
VIH
VOL

2 K R VDD VTN VTP VDD K RVTN VTP

K R 1
K R 1 1 3K R

K R 1VIH VDD K RVTN VTP

2K R

VIL
VOL

2 K R VDD VTN VTP

VDD K RVTN VTP

K R 1 K R 3
K 1VIL VDD K RVTN VTP
R

K R 1

KN
KR
KP
NM L VIL VOL
NM H VOH VIH

Jaeger/Blaloc

MicroelectronicCircu

Chap713

PropagationDelayEstimate

Thetwomodesofcapacitivechargingthatcontributetopropagation
delay

Jaeger/Blaloc

MicroelectronicCircu

Chap714

PropagationDelayEstimate
PHL
RonN

VH VTN
RonN C ln 4
VH VL
1

K n VH VTN

2VTN
1

VH VTN

PHL PLH
p
PHL
2

Ifitisassumedtheinverterinsymmetrical,
(W/L)P=2.5(W/L)N,thenPLH = PHL
Jaeger/Blaloc

MicroelectronicCircu

Chap715

RiseandFallTimes
Theriseandfalltimesaregivenbythefollowing
expressions:

t f 2 PHL
t r 2 PLH
Jaeger/Blaloc

MicroelectronicCircu

Chap716

ReferenceInverterExample
Designareferenceinvertertoachieveadelayof
250pswitha0.1pFloadgiventhefollowing
information:

VDD 3.3V
C 0.1 pF
p 250 ps
VTN VTP 0.75V
Jaeger/Blaloc

MicroelectronicCircu

Chap717

ReferenceInverterExample
Assumingtheinverterissymmetricalandusing
thevaluesgiveninTable7.1:

A
K 25 2
V
A
'
K p 10 2
V
p PHL PLH 250 ps
'
n

Jaeger/Blaloc

MicroelectronicCircu

Chap718

ReferenceInverterExample
SolvingforRonN:
PHL

RonN

VDD VTN
ln 4
VDD VL

1
1

2020

Thensolveforthetransistorratios:
W

Jaeger/Blaloc

1
7.77

K n' RonN VDD VTN

1

W
2.5

19.4
1

MicroelectronicCircu

Chap719

DelayofCascadedInverters
Anidealstepwasusedtoderivetheprevious
delayequations,butthisisnotpossibleto
implement
ByusingputtingthefollowingcircuitinSPICE,it
ispossibletoproducemoreaccurateequations

Jaeger/Blaloc

MicroelectronicCircu

Chap720

DelayofCascadedInverters
Theoutputofthepreviouscircuitlookslikethefollowing
anitcanbeseenthatthedelayforthenonidealstepinput
isapproximatelytwicethantheidealcase:

PHL 2 RonN C

PLH 2 RonP C

Jaeger/Blaloc

MicroelectronicCircu

V V
ln 4 DD TN
VDD VL

1
1

VDD VTP
1
1
ln 4
V
H

Chap721

StaticPowerDissipation
CMOSlogicisconsideredtohavenostaticpower
dissipation
SincetheROFFofthetwotransistorsisverylarge,
theDCcurrentdrivingacapacitiveloadiszero
ThisisnotcompletelyaccuratesinceMOS
transistorshaveleakagecurrentsassociatedwith
thereversebiaseddraintosubstrateconnections
Jaeger/Blaloc

MicroelectronicCircu

Chap722

DynamicPowerDissipation

Therearetwo
componentsthatadd
todynamicpower
dissipation:
1) Capacitiveload
chargingata
frequencyfgiven
by:PD=CVDDf
2) Thecurrentthat
occursduring
switchingwhichcan
beseeninthefigure
Jaeger/Blaloc

MicroelectronicCircu

Chap723

PowerDelayProduct
Thepowerdelayproductisgivenas:

PDP Pav P
2
Pav CVDD
f

1
f
T

Thefigureshowsasymmetrical
inverterswitchingwaveform

2t r 2 2 P
T t r t a t f tb

5 P
0.8
0.8
2
2
CVDD
CVDD
PDP
P
5 P
5

Jaeger/Blaloc

MicroelectronicCircu

Chap724

CMOSNORGate

CMOSNORgate
implementation
Jaeger/Blaloc

ReferenceInverter

MicroelectronicCircu

Chap725

CMOSNORGateSizing
Whensizingthetransistors,itisidealtokeepthe
delaytimesthesameasthereferenceinverter
Toaccomplishthis,theonresistanceonthe
PMOSbranchoftheNORgatemustbethesame
asthereferenceinverter
ForatwoinputNORgate,the(W/L)pmustbe
madetwiceaslarge
Jaeger/Blaloc

MicroelectronicCircu

Chap726

CMOSNORGateBodyEffect
SincethebottomPMOSbodycontactisnot
connectedtoitssource,itsthresholdvoltage
changesasVSBchangesduringswitching
OncevO=VHisreached,thebottomPMOSisnotaffected
bybodyeffect,thusthetotalonresistanceofthePMOS
branchisthesame
However,therisetimeissloweddowndueto|VTP|beinga
functionoftime
Jaeger/Blaloc

MicroelectronicCircu

Chap727

TwoInputNORGateLayout

Jaeger/Blaloc

MicroelectronicCircu

Chap728

ThreeInputNORGateLayout
Itispossibletoextendthissamedesigntechniquetocreate
multipleinputNORgates

Jaeger/Blaloc

MicroelectronicCircu

Chap729

ShorthandNotationforNMOSand
PMOSTransistors

Jaeger/Blaloc

MicroelectronicCircu

Chap730

CMOSNANDGates

CMOSNANDgate
implementation
Jaeger/Blaloc

ReferenceInverter

MicroelectronicCircu

Chap731

CMOSNANDGatesSizing
ThesamerulesapplyforsizingtheNANDgateas
thedidfortheNORgate,exceptfornowthe
NMOStransistorsareinseries
The(W/L)Nwillbetwicethesizeofthereference
invertersNMOS

Jaeger/Blaloc

MicroelectronicCircu

Chap732

MultiInputCMOSNANDGates

Jaeger/Blaloc

MicroelectronicCircu

Chap733

ComplexCMOSLogicGateDesign
Example
DesignaCMOSlogicgatefor(W/L)p,ref=5/1andfor(W/L)n,ref=2/1that
exhibitsthefunction:Y=A+BC+BD
Byinspection(knowingY),theNMOSbranchofthegatecandrawn
asthefollowingwiththecorrespondinggraph,whileconsideringthe
longestpathforsizingpurposes:

Jaeger/Blaloc

MicroelectronicCircu

Chap734

ComplexCMOSLogicGateDesign
Example
Byplacingnodesintheinteriorofeacharc,plustwomoreoutsidethe
graphforVDD(3)andthecomplementaryoutput(2),thePMOS
branchcanberealizedasshownontheleftfigure
Connectallofthenodesinthemannershownintherightfigure,and
theNMOSarcthatPMOSarcintersectshavethesameinputs

Jaeger/Blaloc

MicroelectronicCircu

Chap735

ComplexCMOSLogicGateDesign
Example
FromthePMOS
graph,thePMOS
branchcannowbe
drawnforthefinal
CMOSlogicgate
whileonceagain
consideringthe
longestPMOSpath
forsizing

Jaeger/Blaloc

MicroelectronicCircu

Chap736

ComplexCMOSGatewithaBridging
TransistorDesignExample
DesignaCMOSgatethatimplementsthefollowinglogicfunction
usingthesamereferenceinvertersizesasthepreviousexample:
Y=AB+CE+ADE+CDB
TheNMOSbranchcanberealizedinthefollowingmannerusing
bridgingNMOSDtoimplementY.ThecorrespondingNMOSgraph
isshowntotheright.

Jaeger/Blaloc

MicroelectronicCircu

Chap737

ComplexCMOSGatewithaBridging
TransistorDesignExample
Byusingthesametechniqueasbefore,thePMOS
graphcannowbedrawn

Jaeger/Blaloc

MicroelectronicCircu

Chap738

ComplexCMOSGatewithaBridging
TransistorDesignExample
ByusingthePMOS
graphthePMOS
branchcannowbe
realizedasthe
following(considering
thelongestpathfor
sizing)

Jaeger/Blaloc

MicroelectronicCircu

Chap739

MinimumSizeGateDesignand
Performance
WithCMOStechnology,thereisaarea/delay
tradeoffthatneedstobeconsidered
Ifminimumfeaturesizedareusedforboth
devices,thenthePLH will be decreased
compared to the symmetrical reference
inverter

Jaeger/Blaloc

MicroelectronicCircu

Chap740

MinimumSizeComplexGateand
Layout
Thefollowingshowsthelayoutofacomplexminimumsize
logicgate

Jaeger/Blaloc

MicroelectronicCircu

Chap741

DynamicDominoCMOSLogic
OnetechniquetohelpdecreasepowerinMOS
logiccircuitsisdynamiclogic
Dynamiclogicusesdifferentprechargeand
evaluationphasesthatarecontrolledbyasystem
clocktoeliminatethedccurrentpathinsingle
channellogiccircuits
EarlyMOSlogicrequiredmultiphaseclocksto
accomplishthis,butCMOSlogiccanbeoperated
dynamicallywithasingleclock
Jaeger/Blaloc

MicroelectronicCircu

Chap742

DynamicDominoCMOSLogic
Thefiguredemonstratesthebasicconceptof
dominoCMOSlogicoperation

Jaeger/Blaloc

MicroelectronicCircu

Chap743

SimpleDynamicDominoLogicCircuit

Jaeger/Blaloc

MicroelectronicCircu

Chap744

DynamicDominoCMOSLogic
ItshouldbenotedthatdominoCMOScircuitsonly
producetruelogicoutputs,butthisproblemcanbe
overcomebyusingregistersthathavebothtrueand
complementedoutputtocompletethefunctionshownby
thefollowing

Jaeger/Blaloc

MicroelectronicCircu

Chap745

CascadeBuffers
Insomecircuit,thelogicmustbeabletodrive
largecapacitances(10to50pF)
Bycascadinganevennumberofincreasinglarger
inverters,itispossibletodrivetheloads

Jaeger/Blaloc

MicroelectronicCircu

Chap746

CascadeBuffers
Thetaperfactor determines the increase of the cascaded inverterssizeinmannershownofthepreviousimage.

whereCoistheunitinvertersloadcapacitance
Thedelayofthecascadedbufferisgivenbythefollowing:

CL

Co
N

CL

B N
Co
Jaeger/Blaloc

1/ N

Whereo is the unit inverters

propagation delay

MicroelectronicCircu

Chap747

OptimumDesignofCascadedStages
Thefollowingexpressionscanaidinthedesignof
anoptimumcascadedbuffer
N opt

Jaeger/Blaloc

CL

ln
Co
1
CL
Co

opt

CL

Co

Bopt

CL
o
ln
Co

ln

MicroelectronicCircu

Chap748

TheCMOSTransmissionGate
TheCMOS
transmissiongate
(Tgate)isoneofthe
mostusefulcircuitsfor
bothanaloganddigital
applications
Itactsasaswitchthat
canoperateuptoVDD
anddowntoVSS

Jaeger/Blaloc

MicroelectronicCircu

Chap749

TheCMOSTransmissionGate
Themainconsiderationthatneedstobe
consideredistheequivalentonresistancewhichis
givenbythefollowingexpression:
REQ

Jaeger/Blaloc

Ronp Ronn
Ronp Ronn

MicroelectronicCircu

Chap750

CMOSLatchup
ThereisonemajordownfalltotheCMOSlogic
gateLatchup
Therearemanysafeguardsthataredoneduring
fabricationtosuppressthis,butitcanstilloccur
undercertaintransientorfaultconditions

Jaeger/Blaloc

MicroelectronicCircu

Chap751

CMOSLatchup
Latchupoccursdueparasiticbipolartransistors
thatexistinthebasicinverterasshownbelow

Jaeger/Blaloc

MicroelectronicCircu

Chap752

CMOSLatchup

Jaeger/Blaloc

MicroelectronicCircu

Theconfigurationof
thesebipolar
transistorscreatea
positivefeedback
loop,andwillcause
thelogicgateto
latchupasshownto
theleft
Byusingheavily
dopedmaterialwhere
RnandRpexist,there
resistancewillbe
loweredthereby
reducingthechance
oflatchupoccurring

Chap753

EndofChapter7

Jaeger/Blaloc

MicroelectronicCircu

Chap754