Beruflich Dokumente
Kultur Dokumente
Scaling
Moores Law
3D VLSI
The beginning
Microprocessors are essential to many of the products
we use every day such as TVs, cars, radios, home
appliances and of course, computers. Transistors are
the main components of microprocessors.
At their most basic level, transistors may seem
simple. But their development actually required many
years of painstaking research. Before transistors,
computers relied on slow, inefficient vacuum tubes
and mechanical switches to process information. In
1958, engineers managed to put two transistors onto a
Silicon crystal and create the first integrated circuit,
which subsequently led to the first
microprocessor.
MOSFET
performance
improves as size is
decreased:
shorter switching
time, lower power
consumption.
Significant Breakthroughs
Transistor size: Intels research labs have recently shown the worlds smallest
transistor, with a gate length of 15nm. We continue to build smaller and smaller
transistors that are faster and faster. We've reduced the size from 70 nanometer to 30
nanometer to 20 nanometer, and now to 15 nanometer gates.
Manufacturing process: A new manufacturing process called 130 nanometer process
technology (a nanometer is a billionth of a meter) allows Intel today to manufacture
chips with circuitry so small it would take almost 1,000 of these "wires" placed sideby-side to equal the width of a human hair. This new 130-nanometer process has
60nm gate-length transistors and six layers of copper interconnect. This process is
producing microprocessors today with millions of transistors and running at multigigahertz clock speeds.
Wafer size: Wafers, which are round polished disks made of silicon, provide the base
on which chips are manufactured. Use a bigger wafer and you can reduce
manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches)
diameter silicon wafer size, up from the previous wafer size of 200mm (about 8
inches).
Microscopic issues
ultra-high speeds
power dissipation and
supply rail drop
growing importance of
interconnect
noise, crosstalk
reliability,
manufacturability
clock distribution
Macroscopic issues
time-to-market
design complexity
(millions of gates)
high levels of
abstractions
design for test
reuse and IP, portability
systems on a chip (SoC)
tool interoperability
Year
Tech.
Complexity
Frequency
Staff Size
Staff Costs
1997
0.35
13 M Tr.
400 MHz
210
$90 M
1998
0.25
20 M Tr.
500 MHz
270
$120 M
1999
0.18
32 M Tr.
600 MHz
360
$160 M
2002
0.13
130 M Tr.
800 MHz
800
$360 M
Integrated Circuits
What are shown on previous diagrams cover only the so called front end
processing fabrication steps that go towards forming the devices and
interconnections between these devices to produce the functioning IC's. The
end result are wafers each containing a regular array of the same IC chip or
die. The wafer then has to be tested and the chips diced up and the good chips
mounted and wirebonded in different types of IC package and tested again
before being shipped out.
Moores Law
Moores Law:
Moores Law
In 1965, Gordon Moore predicted that the number of transistors that can be
integrated on a die would double every 18 to 14 months
i.e., grow exponentially with time
Amazing visionary million transistor/chip barrier was crossed in the 1980s.
2300 transistors, 1 MHz clock (Intel 4004) - 1971
42 Million, 2 GHz clock (Intel P4) - 2001
140 Million transistor (HP PA-8500)
Moores Law
Ever since the invention of integrated circuit, the smallest feature size has been
reducing every year. Currently (2002) the smallest feature size is about 0.13
micron. At the same time the number transistors per chip is increasing due to
feature size reduction and increase in chip area. Classic example is the case of
memory chips: Gordon Moore of Intel in early 1970s found that: density (bits per
chip) growing at the rate of four times in 3 to 4 years - often referred to as Moores
Law. In subsequent years, the pace slowed down a bit, data density has doubled
approximately every 18 months current definition of Moores Law.
what then?
Paradigm shift needed in fabrication process
Recurring Costs
cost of die + cost of die test + cost of packaging
variable
cost
=
---------------------------------------------------------------final test yield
cost of wafer
cost of die = ----------------------------------dies per wafer die yield
(wafer diameter/2)2
wafer diameter
dies
per
wafer
=
---------------------------------
--------------------------die area
2 die area
die yield
Yield Example
Example
100
10
8080
8008
4004
8086
8085
286
386
P6
486 Pentium proc
1
1970
1980
1990
Year
Courtesy, Intel
2000
2010
Clock Frequency
Lead microprocessors frequency doubles every 2 years
10000
2X every 2 years
Frequency (Mhz)
1000
P6
100
486
10
8085
1
0.1
1970
8086 286
Pentium proc
386
8080
8008
4004
1980
1990
Year
Courtesy, Intel
2000
2010
Metal
layers
Line
width
Dies/ Yield
wafer
Die
cost
386DX
0.90
$900
1.0
43
360
71%
$4
486DX2
0.80
$1200
1.0
81
181
54%
$12
PowerPC
601
0.80
$1700
1.3
121
115
28%
$53
HP PA
7100
0.80
$1300
1.0
196
66
27%
$73
DEC
Alpha
0.70
$1500
1.2
234
53
19% $149
Super
SPARC
0.70
$1700
1.6
256
48
13% $272
Pentium
0.80
$1500
1.5
296
40
9% $417
VLSI
Origins of VLSI
Advantages of 3D VLSI
Speed - the time required for a signal to travel between the functional circuit
blocks in a system (delay) reduced.
Delay depends on resistance/capacitance of interconnections
resistance proportional to interconnection length
Advantages of 3D VLSI
Advantages of 3D VLSI
Power consumption
power used charging an interconnect capacitance
P = fCV2
power dissipated through resistive material
P = V2/R
capacitance/resistance proportional to length
reduced interconnect lengths will reduce power
Advantages of 3D VLSI
Advantages of 3D VLSI