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Chapter 4
1
Combinational Logic
Outline
Combinational Circuits
Analysis
Design
Combinational Circuits
Recall
Combinational circuit
Combinational Circuits
Sequential Circuits
4
Combinational Circuit
Analysis
Circuit analysis
Combinational Circuit
Analysis
Analysis steps
1.
2.
3.
Combinational Circuit
Analysis
Analysis steps
1.
2.
3.
Combinational Circuit
Analysis
Substitution
T1 ( xy )
T2 ( xT1 )
T3 ( yT1 )
F (T2T3 ) (( xT1 )( yT1 ))
xT1 yT1 x( xy ) y ( xy )
x( x y) y ( x y)
xx xy xy yy
xy xy x y
8
Here
T2 = ABC
T1 = A+B+C
F2 = AB + AC + BC
T3 = F2 T1
F 1 = T 3 + T2
10
1.
2.
3.
4.
5.
Issues to consider
Number of gates
Gate inputs
Propagation delay
Number of interconnections
11
12
4 inputs: A, B, C, D
4 outputs: w, x, y, z
13
14
15
Step 4: Simplification
z = D
y = CD+CD
= CD+(C+D)
x = BC+BD+BCD
= B(C+D)+BCD
= B(C+D)+B(C+D)
w = A+BC+BD
= A+B(C+D)
17
Binary Adders
Half adder adds two bits and generates result and carry
Full adder considers carry input in addition to half adder
Two half adders make one full adder
18
Specification
Design a circuit that adds two bits and generates the sum and a carry
Input / Output
19
Specification
Input/Output
Design a circuit that adds two bits and generates the sum and a carry
Two inputs: x, y
Two output: S (sum), C (carry)
Functionality
20
Specification
Input/Output
Design a circuit that adds two bits and generates the sum and a carry
Two inputs: x, y
Two output: S (sum), C (carry)
Functionality
21
22
23
Full Adder
Specifications
Input/output
Truth table
24
Full Adder
Specifications
Input/output
Truth table
25
Full Adder
26
Full Adder
27
Full Adder
Circuit
28
Observations
x+y+z = (x+y) + z
Carry can occur when adding x+y and when adding z
30
31
Carry-Lookahead Adder
Recall
For the design of the parallel adder to work, the signal must propagate
through the gates before the correct output sum is available
Total propagation time = propagation delay of a
typical gate x the number of gates
Lets look at S3
33
Carry-Lookahead Adder
S i = P i Ci
Ci+1 = Gi + Pi Ci
34
Carry-Lookahead Adder
Si = P i Ci
Ci+1 = Gi + Pi Ci
C0 = input carry
C 1 = G 0 + P0C 0
C 3 = G 2 + P 2 C 2 = = G 2 + P 2G 1 + P 2 P 1 G 0 + P 2P 1P 0C 0
Carry-Lookahead Adder
Circuit
SOP form
Only 2 stages
36
Complete adder
Drawback?
Increasing complexity of
lookahead logic for more
bits
37
Subtraction
Do we need subtractors?
Actually not
Subtraction can be done using adders
N M = N + (2s complement of M)
38
Subtraction
Input carry
Can we do something ?
Yes
39
Subtraction
Can we do something ?
Yes
XOR gate
x 0 = x (use for Addition)
x 1 = x (use for Subtraction)
40
Binary Subtractor
Adder/Subtractor circuit
41
Overflow
End carry
Called overflow
Needs to be detected by computer system
If carry into sign position and out of sign position differ, then overflow
42
Overflow Conditions
Overflow conditions
Overflow can happen only when both numbers have same sign, and
If carry into sign position and out of sign position differ
43
44
BCD Adder
How to begin?
Truth table
Can we use existing circuit?
Binary adder
45
46
47
BCD Adder
How to implement?
48
BCD Adder
49
BCD Adder
50
Multiplier
AND gate
2-bit multiplier
51
Multiplier
Circuit diagram
52
Multiplier
J x K gates
J=3, K=4
J + K bits
53
Magnitude Comparator
Which gate?
XNOR (Equivalence)
Magnitude Comparator
Case 1: A > B
Functionality (4-bits)
For A > B
Magnitude Comparator
Case 2: A < B
Functionality
(A = B) = x3x2x1x0
x 3x 2A 1 B 1 + x 3x 2x 1A 0B 0
x3x2A1B1 + x3x2x1A0B0
Encoders (Enc)
Decoders (Dec)
Multiplexers (Mux)
De-multiplexers (DeMux)
Tri-state logic
57
58
Instruction Management
59
Decoder
Applications
Binary-to-octal decoder
Memory address selection
Selection of any kind
60
Decoder
61
Decoder: Circuit
If x y z
If x y z
Sequence of minterms
Combine variables to
minterms
62
Advanced Decoder
Example:
63
Advanced Decoder
Active-high enable
NO
Absence of enable
64
Decoders: Example
65
Encoders
Input: 2n lines
Output: n bits
Output is binary coding of input that is 1
66
Encoders
x = D4 + D5 + D6 + D 7
y = D2 + D3 + D6 + D 7
z = D1 + D3 + D 5 + D 7
67
Encoders: Problems
Example
x = D4
+ D5 +
D6 + D7
y = D2
+ D3 +
D6 + D7
z = D1
+ D3 +
D5 + D7
68
Priority Encoder
D3
69
Priority Encoder
Valid bit V = D0 + D1 + D2 + D3
70
Priority Encoder
Circuit diagram
x = D 2 + D3
y = D 3 + D 1D2
V = D0 + D1 + D2 + D 3
71
Multiplexer (MUX)
Input
Output
2n lines
1 line
72
Multiplexer (MUX)
Example
2-to-1 MUX
How to design?
4-to-1 MUX
Selection code directs input
73
4-to-1 MUX
What are the values of Y?
74
Multiplexer (MUX)
75
Concept
76
Example
F(x,y,z) = (1,2,6,7)
Truth table
77
78
Example
F(x,y,z) = (1,3,4,11,12,13,14,15)
79
80
Example:
Expressions
81
82
Demultiplexer (DeMUX)
Input
Output
Data bit
n selection lines
2n lines
Three state:
0 or 1 Boolean value
High impedance, Z state
2-to-1 MUX
85
Problems
86
Problems
87
Problems
88
Problems
89
Problems
90
Problems
91