I/O & ESD Design

Byron Krauter, IBM

Mark McDermott

Outline
I/O Signaling Requirements
Basic CMOS I/O and Receiver Design
Real-world CMOS I/O and Receiver Design
Impedance Matching & Slew Rate Control
Mixed Voltages
ESD and other extreme conditions

Increasing Bandwidth

Source Synchronous I/O or Co-transmitted Clock

Pipelined Bus or Bus Pumping
Dual Data Rate
Simultaneous Bi-Directional
Pattern Based Driver Compensation

Transmission Lines

05/18/16

I/O Signaling
There are basically two forms of signaling used for
input/output applications
Single Ended
Differential

In single-ended signaling one wire carries a varying

voltage that represents the signal, while the other
wire is connected to a reference voltage, usually
ground.
Single ended signaling is less expensive to implement than
differential, but its main limitations are that it lacks the
ability to reject noise caused by differences in ground voltage
level between transmitting and receiving circuits.

Differential signaling uses two complementary

signals sent on two separate wires.
Able to reject common-mode noise
More expensive to implement from both a wire perspective as
well as the transmit & receive logic.
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Single Ended vs. Differential Signaling

Single Ended

Differential

05/18/16

Single-ended Bus Signaling Standards

Courtesy Mike Morrow, UW

05/18/16

Differential Bus Signaling Standards

Courtesy Mike Morrow, UW

05/18/16

Complications
Pin Count Limitations
Bi-directional signaling
Simultaneous switching noise

Transmission Line Behavior

Limited net topologies work

Terminations required
Skin effect
Dielectric loss

Other Noises
Reflections
Discontinuity noise
Crosstalk and connector noise

Mixed Voltages
ESD and Other Handling Complications

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Basic CMOS I/O and Receiver

Design

Bidirectional CMOS I/O Buffer

enable_b

Pad

data

enable
0
1
data

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Hi Z

Hi Z

CMOS Input Receiver

Any two input gate that
Has good noise immunity
Provides on-chip control when off-chip inputs float

Example: two input NAND

Pad
data

05/18/16

enable
0
1

enable
out

data

10

Real-world CMOS I/O Design

Real-world CMOS I/O Design

Output Impedance Control
Slew Rate Control
Mixed Voltage Designs
Input Design for Higher Voltages
Output Design for Higher Voltages
Dual Power Supplies
Floating Well Designs
Open Source Signaling

Other Circuits
Differential I/O Circuits
Hysteresis Receivers

ESD Circuits

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12

Output Impedance Control

Device resistances are too variable for source
termination
Devices are non-linear
Variations due to VDD, Temp, and process variations
alone are >2X in linear region!

Output stages must be designed to reduce this

variation
On-chip resistors designs
Logically tunable designs

05/18/16

Impedance Control Using On-Chip

Resistors

Given a precise on-chip resistor, this design

provides the best impedance control

enable_b
Pad
data

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14

Tunable Impedance Control

Stacked device settings can be preset or
dynamically controlled

p1

p2

p3

enable_b

Pad

data

n1

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n2

n3

15

Slew Rate Control

Output stage slew rate is controlled to reduce
noise
Cross talk noise
Simultaneous switching noise
Reflections at discontinuities

Slew rate control is accomplished by controlling

the pre-driver delay and/or pre-driver strength

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16

Slew Rate Control

Output stage is divided and pre-drive signal is
designed to sequentially arrive at the different
sections

enable_b

Pad

data

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17

Slew Rate Control & Impedance Control

Pre-driver design might even permit crossover
currents to guarantee impedance even during
switching

enable_b
data

Pad

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Feedback Slew Rate Control I/O Buffer

enable_b
Pad
data

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19

Feedback Slew Rate Control I/O Buffer

(Patents)

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20

Mixed Voltage Designs

Needed when chips have different supply
voltages
Low voltage circuits can be damaged by high
voltage inputs
High voltage circuits suffer delay & noise
problems when receiving low voltage signals
VDD_1

Bi-directional
I/O Buffers

newer
technology

older
technology

VDD_1 < VDD_2

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VDD_2

Input Design for Higher Voltages

Modifications for gate oxide & ESD protection

Receiving Same Level

ESD Diodes

Pad

Receiving Higher Level

ESD Diodes

Pad

change beta ratio

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Dual Supply Designs

Separately power I/O circuits at a lower voltage
No additional process steps required
Extra design to avoid performance penalty
ESD & simultaneous switching noise compromised

VDD_1
newer
technology

05/18/16

Bi-directional
I/O Buffers

VDD_1

VDD_2

older
technology

Output Stage at a Lower Voltage

Slow rising delay due to low overdrive on PMOS
Reduced drive = reduced noise immunity on
NAND receiver
Vdd2

enable_b

Vdd1

Vdd1 or Vdd2
ESD Diodes

Pad
data

inhibit
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24

Output Stage at a Lower Voltage

Improve rising delay with NMOS pull up
Change p/n beta ratio on NAND to lower switch
point
1.8 Volts

enable_b

1.2 Volts

1.2 or 1.8 Volts

ESD Diodes

Pad
data

Inhibit_b
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change beta ratio

25

Dual Supply Designs

Separately power the I/O circuits at a higher
voltage
More complicated circuits
ESD & simultaneous switching noise compromised

1.2 Volts
1.8 Volts
newer
technology

05/18/16

Bi-directional
I/O Buffers

1.8 Volts
older
technology

26

Output Stage at a Higher Voltage

Slow rising delay due to low overdrive on PMOS
Reduced drive = reduced noise immunity on
NAND receiver
Vdd2

Vdd1

enable_b

Level
Shifte
r
Vbias

data
Vdd1

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Vdd2

Pad

Floating Well Designs

Enabled output stage outputs a lower voltage
-> Vdd1
Disabled output stage tolerates higher voltage
Vdd1
Vdd1
-> Vdd2

enable

Vdd1

data
Vdd1

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Pad

Open Drain Signaling

Avoids complexity of multiple chip power
supplies
Off-chip termination resistors pull net up
On-chip NMOS devices pull net down

Increases transmission line design complexity

Wired OR functionality
Driving Chip

Vtt

Vtt
CL

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CL

CL

CL

CL

29

Other Circuits
Differential I/O Circuits

Reduces simultaneous switching noise

Improves receiver common mode noise immunity
Receives smaller signal levels
Pseudo to full differential possible

Hysteresis Receivers
High noise immunity
Excellent for low-speed asynchronous test & control
signals

Hold Clamps

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30

Differential Output Buffers

Pseudo Differential Outputs
out
Differential Outputs
VDD

out

out

out

Vbias

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31

Differential Transmission Lines

Pseudo = two lines

Zo
Zo

Differential = coupled pair

Zeff < Zo
coupled

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Zeff < Zo

32

Differential Far End Termination

Pseudo Differential Termination
Vtt

R = Zo

Vtt

R = Zo
Differential Termination

R = 2 Zo

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33

Differential Receivers
Pseudo Differential Receiver
out
Differential Receiver
VDD

out

out

out

Vbias

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34

Self Biased Differential Receiver

Combines best of NMOS and PMOS differential
receivers

VDD

VDD

out out

Pbias

out out

Nbias
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35

Self Biased Differential Receiver

Combines best of NMOS and PMOS differential
receivers
Rail to rail output swing
Excellent common mode noise rejection
VDD

out

or reference

(Bazes, JSSC 91)

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36

Hysteresis Input Receivers

Separates rising & fall edge dc transfer curves
weak feedback inverter
Pad

Vin

Vout
inhibit

Pad

Vin

Vout

Vout

falling

rising
AND only
Vin

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37

Hold Clamps
Weak clamps hold tri-stated source terminated
nets

Pad

weak feedback inverter

VDD
I/O

Stronger clamps will actively terminate the net

Can be slower than passive termination schemes
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38

ESD Design
Pins subjected to ESD (electrostatic discharge)
events during test & handling
Over-voltages can also occur during functional
operation
System power-on
Hot-plugging

ESD discharge can occur between any two pins

I/O to I/O
I/O to VDD or Gnd

Pins are measured against standard ESD tests

Human body model
Machine model
Charged Device Model

ESD performance depends on many parameters

other circuits dont care about
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39

ESD Circuits
Non-breakdown based circuits
Diodes
Bipolar Junction Transistor
MOSFET

Breakdown based circuits

Thick Field Oxide Device
SCR (silicon controlled rectifier)

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Dual Diode ESD Circuits

Mixed voltage design

Single Supply Design

ESD Diodes

Pad

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ESD Diodes

Pad

41

FET ESD Circuits: non-breakdown mode

NMOS in diode
configuration
ESD Diodes

Pad

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42

FET ESD Circuits: breakdown mode

ESD Diodes

Pad

second
breakdow
n
I
NMOS protects
by clamping voltage
after device snapback

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Vgs > Vt

snapback

43

Diode ESD Circuits

FET devices are parasitic npn & pnp bipolar
circuits
vertical pnp device to substrate

horizontal npn device to guard rings (before trench isolation)

low vdd to gnd impedance to due on-chip capacitance

provide additional discharge paths

ESD Diodes

Pad

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ESD bipolar devices

Pad

44

Parasitic Bipolar Circuits

FET devices are parasitic npn & pnp bipolar
circuits
vertical pnp device to substrate

05/18/16

ESD Test Models

Human Body Model
Requirements 2 - 4 kVolts
Positive or negative discharge between any two pins

VHBM

R = 1.5 K

DUT
C = 100 pF

ipeak = VHBM/1500
i(t)

t = 2-10 nsec
05/18/16

time

ESD Test Models

Machine Model
Requirements 200 - 400 Volts
Positive or negative discharge between any two pins

L = 0.5 - 0.75 H

VMM

DUT

R < 8.5

C = 200 pF

05/18/16

ESD Performance Factors

Diode symmetry is important
Bipolar conduction increases with temperature
Hot spots conduct more, heat up more, conduct more,
and finally burn out

Layout corners are rounded to reduce electric

fields
Decoupling capacitance needed between all
supplies
Functional performance requirements impose
ESD size & load capacitance constraints
Parasitic bipolar effects abound
Breakdown clamps dont scale
Virtual supply node needed for multi-VDD
designs
05/18/16

Increasing Bandwidth

05/18/16

Common Clock Transfers

Chip to chip transfers controlled by common
bus clock
Equal length card routes to each chip & on-chip
PLLs minimize clock skew
Chip A

PLL

PLL

Chip B

clock
source
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50

Common Clock Transfers

Cycle time to meet setup time
max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle

Chip A

PLL

Tdrive

Ttof

TAclk

Treceive

PLL
Tclk - A

Tclk - B

Tsetup

TBclk
Chip B

clock
source
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51

Source Synchronous I/O

Send source clock with source data
Resolve clock phase differences with 1, 2, & 3

Chip B

Chip A

PLL

3
1

PLL

clock
source
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52

Bus Pumping
With Ttof > Tcycle, multiple bits are present on
the wire

Chip B

Chip A

PLL

3
1

PLL

clock
source
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53

Dual Data Rate

Conventional source synchronous design
Data launched & captured on single clock edge
Clock switches at f
Maximium data rate = 1/2 * f

Dual data rate - if clock can switch at f, why not

data?
Data is launched & captured on both clock edges
Clock switches f
Maximum data rate = f
Conventional

Dual Data Rate

Clock
Data
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54

Simultaneous Bidirectional Signaling

Two chips send & receive data simultaneously
on a point to point net
Waveforms superimpose on the transmission
line
Each chip selects its receiver reference voltage
based on the data it sent
Sending data is subtracted from total waveform
Chip A
3/4 VDD
1/4 VDD

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Chip B
3/4 VDD
1/4 VDD

55

Pattern Based Driver Compensation

Incident waveforms along a long-lossy lines
attenuate
Slow RC like response to final level
Rs = Zo
Vs

f
where f = length / velocity

With complex impedance and propagation constant

high speed wavefront decays exponentially
1/2
(1- e-R*length/2Zo)

05/18/16

56

Pattern Based Driver Compensation

Adjust driver strength based on bits sent in
earlier cycles
Example: When driving low to high
Drive harder if previous bits sent = 00
Drive weaker if previous bits sent = 10

Without Compensation
1

1 0 0

With Compensation
1

1 0 0

Receiver
Switch Point

Drive harder
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57

Increasing Bandwidth
Preceding techniques cannot be achieved
through clever circuit design alone
Requires good packaging technology & net
design

05/18/16

Good termination
Minimal capacitive & inductive discontinuities
Low cross-talk
Low simultaneous switching noise

58

Backup

Transmission Line Behavior

But First A Few Words on

Common Ground
Interconnect Models

Example - Two Wires & One Source

Twin lead transmission line modeled as a single
section and driven by a Thevenin source

Rsource

0.5*Cwire

L11

M12

L22

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Rwire

0.5*Cwire

Rwire

62

Example - Two Wires & One Source

Being concerned with local potentials only (i.e.
capacitor potentials) inductances and
resistances can be combined
Rsource

L11

0.5*Cwire

Rsource

0.5*Cwire

05/18/16

Rwire

L22

Rwire

0.5*Cwire

M12

L11+ L22 - 2*M12

2*Rwire

0.5*Cwire

63

Example - Three Wires & Two Sources

When multiple wires form a cutset, treat one
wire as a reference lead and fold it into the
other wires*.
Rs1

L11

0.5*C1g

R1

M1g

0.5*C1g
Rg

M2g

0.5*C2g

Cutse
t
0.5*C12

0.5*C12 M12 Lgg

0.5*C2g
Rs2

L22

R2

* Brian Young, Digital Signal Integrity: Modeling and Simulation

with Interconnects and Packages
05/18/16

64

Example - Three Wires & Two Sources

Resulting loop impedance model for three
parallel wires driven by two Thevenin sources
mutual resistances
L11+Lgg-2M1g

Rs1

R1+Rg

v1
i2Rg

0.5*C1g

0.5*C1g

M12-M1g-M2g+Lgg

0.5*C12

v2
i1Rg
L22+Lgg-2M1g

Rs2
0.5*C1g

05/18/16

R2+Rg

0.5*C12

0.5*C2g

65

Transmission Line Behavior

On and off chip signals can always be modeled
with lumped RLC circuits
Wire segments are modeled with or t segments

L, R, C, and G can be frequency dependent

But inductance is not always important
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66

Transmission Line Behavior

Inductance is important when
Driver source impedance Rs is low
Rs < Zo
where Zo = characteristic impedance of line

Driver rise time r is fast

r < 2.5 f

where f = time of flight

Line loss is low

R << jL or (R / 2Zo) << 1

Can be restated for point to point

RsCtot <

05/18/16

Wave front
decays exponentially
withas
this constant
nets

1/2 RlineCline < f

67

When Inductance is Important

Nets ring and net delays become unpredictable
unless:
Net topologies are constrained
Point to point nets
Periodically loaded nets
Near and far end clusters

Nets are driven appropriately

Not to strong and not to weak
Not to fast and not to slow

Nets are terminated appropriately

Source termination
Far end termination

Resistance to VDD or Gnd or any Thevenin Voltage

AC termination = RC circuit
Active hold clamps
Diode or Schottky diode clamps

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68

Transmission Line Behavior

Perfectly source terminated point to point, lossless net
f

Rs = Zo

Zo =

L
C

f = LC
far end

V(t)

near end

f
time
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69

Transmission Line Behavior

Under driven point to point, loss-less net

Rs = 3Zo

Zo =

L
C

f = LC
Approximates
RC step response

far end

V(t)
near end

time
05/18/16

70

Transmission Line Behavior

Over driven point to point, loss-less net

Rs = 1/3 Zo

Zo =

L
C

f = LC
far end

V(t)
near end

time
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71

Reflection and Transmission

With incident wave Vinc traveling down the line
Voltage reflection coefficient

v =

ZL - Zo
ZL+ Zo

v =

1,

ZL=

0,

ZL= Zo

-1,

ZL= 0

Voltage transmission coefficient

v = 1 + v =

05/18/16

2ZL
ZL+ Zo
72

Equivalent Circuits Along Line

Rs
Vs

near end
+
Zo Vinc
Zo
2Vinc

along line
Zo

Zdiscontinuity
Zo

2Vinc

05/18/16

far end
ZL

73

Discontinuities Along Line

Rs = Zo

1
C

Vs

Rs = Zo
Vs

05/18/16

1/2

Vs=1

1/2

1/2 (1- e-2t/ZoC)

Vs=1

1- 1/2(1- e-2Zot/L)

74

Well Behaved Net Topologies

Point to Point Nets

Rs = Zo

Rs << Zo

05/18/16

Source terminated

Far end terminated

Vterm
Rterm Zo

Well Behaved Net Topologies

Periodically Loaded Nets

Source terminated: Near end switches last

Rs = Zeff
CL

With periodic loading

CL

CL

Zeff =

L
C + nCL

f =
05/18/16

L(C+nCL)

CL

Well Behaved Net Topologies

Periodically Loaded Nets

Far end terminated: Near end switches first

Rterm Zeff
Vterm

Rs << Zeff
CL

With periodic loading

CL

CL

Zeff =
f =

05/18/16

CL

L
C + nCL
L(C+nCL)

Well Behaved Net Topologies

Near end (or Star) cluster

Rs = Zo/N

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Well Behaved Net Topologies

Far-end cluster

Rs = Zo/N

05/18/16

Zo/N

Well Behaved Net Topologies

Double far-end terminated bus

Rs << Zo

Vterm

Vterm
CL

05/18/16

CL

CL

CL

CL

Ideal Transmission Lines

I(z)

i
V
C
z
t
V
i
L
z
t

V(z)

V Re [V
Steady State Solution:

where
05/18/16

Ideal
Telegraphers Equation

2V
2V
LC 2
2
z
t

j ( z t )

j (z t )

1
j ( z t )
j (z t )

I Re ( [V e
V e
])
Z
Z=

L
C

= LC
81

Transmission Lines with Loss

Z() =

jL + R
jC
L
(1 - j R/2L)
C

R
Z ( ) Z 0 j
2 C Z0
05/18/16

j =

(jL + R) jC

jLC

(1 - j R/2L)

R
( ) LC
2 Z0
82

Waveforms Along a Low Loss Line

Rs << Zo
Vs

f
where f = length / velocity

With complex impedance & complex propagation constant

high speed wavefront decays exponentially & distorts
1
(1- e-R*length/2Zo)

05/18/16

83

Distortionless Transmission Line

Oliver Heaviside (1887)

G /C R/ L

Z() =

05/18/16

jL + R
jC + G
L
C

j =

(jL + R)(jC + G)
LC ( jRL)

84

Waveforms Along a Distortionless Line

Rs << Zo
Vs

f
where f = length / velocity

With real impedance and complex propagation constant

high speed wavefront decays exponentially but without distortion
1
(1- e-R*length/Zo)

05/18/16

85