Lesson 3

Advanced Topics in VHDL

some of the slides are taken from
http://www.microlab.ch/courses/vlsi/vlsi21.pdf.

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Topics

Hierarchy, Abstraction, and Accuracy

Generics
Configuration
Subprograms, Packages and Libraries
Finite State Machines
I/O Files
Testbench

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Hierarchy, Abstraction, and Accuracy

Structural models simply describe interconnections

Structural models do not describe any form of behavior
Hierarchy expresses different levels of detail
Structural models are a way to manage large, complex
designs
Modern designs have several 10 millions of gates
Simulation time: the more detailed a design is described,
the more events are generated and thus the larger the
simulation time will be needed.

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Generics

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More on Generics
Within a structural model there are two ways in
which the values of generic constants of lower
level components can be specified:
in the component declaration
in the component instantiation

If both are specified, then the value provided by

the generic map() takes precedence.
If neither is specified, then the default value
defined in the model is used.

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Configuration
Structural models may employ different levels of
abstraction.
Each component in a structural model may be
described as a behavioral or a structural model.
Configuration allows stepwise refinement in a
design cycle.
Configuration represents resource binding.
Description-synthesis design method.

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Configuration: Component Binding

Example of binding architectures: A bit-serial
adder.
One of the different architectures must be bound
to the component C1 for simulation
Entity is not bound as interfaces do not change

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Configuration: Default Binding Rules

To analyze different implementations, we simply change
the configuration, compile and simulate.
When newer component models become available we
bind the new architecture to the component
Default binding rules:
If the entity name is the same as the component name, then this
entity is bound to the component.
if there are different architectures in the working directory, the
last compiled architecture is bound to the entity

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Subprograms, Packages and Libraries

VHDL provides mechanisms for structuring
programs, reusing software modules, and
otherwise managing design complexity.
Packages contain definitions of procedures and
functions that can be shared across different
VHDL models.
Packages may contain user defined data types
and constants and can be placed in libraries.
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Overloaded AND Operator

1

2
3

type MVL4 is ('X','0','1','Z');

type MVL4_TABLE is array (MVL4, MVL4) of MVL4;
function "and" (L, R: MVL4) return MVL4 is
constant table_AND: MVL4_TABLE :=
(('X', '0', 'X', 'X'),
('0', '0', '0', '0'),
('X', '0', '1', 'X'),
('X', '0', 'X', 'X'));
begin
return table_AND(L, R);
end "and";
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2
3

Features of Overloading

Values, operators, and subprograms can be

overloaded
How does the compiler differentiate between
overloaded and normal objects?
values? - type marks
operators and subprograms? - parameter and
result profiles

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Overloaded Type Conversion Function

function INTVAL(VAL: MVL4_VECTOR) return INTEGER is

1
variable SUM: INTEGER := 0;
begin
for N in VALLOW to VALHIGH loop
assert not(VAL(N) = X or VAL(N) = Z)
report INTVAL inputs not 0 or 1
2
severity WARNING:
if VAL(N) = 1 then
SUM := SUM + (2**N);
end if;
3
end loop;
return SUM;
end INTVAL;
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Continued
function INTVAL(VAL: BIT_VECTOR) return INTEGER is
variable SUM: INTEGER := 0;
begin
for N in VALLOW to VALHIGH loop
if VAL(N) = 1 then
SUM := SUM + (2**N);
end if;
end loop;
return SUM;
end INTVAL;
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Overloaded + In A Package

PACKAGE math IS
FUCNTION +(1, r: BIT_VECTOR) return INTEGER;
END math;
PACKAGE BODY math is
FUNCTION vector_to_int(S: BIT_VECTOR) RETURN INTEGER IS
VARIABLE result: INTEGER := 0; --- this function is local to
VARIABLE prod: INTEGER := 1; --- the package
BEGIN
3FOR i IN sRANGE LOOP
3
IF s(i) = 1 THEN
result := result + prod;
END IF;
prod := prod * 2;
END LOOP;
RETURN result;
END vector_to_int;

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Continued
FUNCTION +(1, r: BIT_VECTOR) RETURN INTEGER IS
BEGIN
RETURN(vector_to_int(1) + vector_to_int(r));
END;
END math;
USE WORK.math.ALL;
ENTITY adder IS PORT(a, b: IN BIT_VECTOR(0 TO 7);
c: IN INTEGER; dout: OUT INTEGER);
END adder;
ARCHITECTURE test OF adder IS
SIGNAL internal: INTEGER;
BEGIN
internal <= a + b; --- which + ?
dout <= c + internal; --- which + ?
END test;
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Libraries

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Example: Libraries and Packages

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FiniteStateMachinesandVHDL

StateProcesses
StateCoding
FSMTypes
Medvedev
Moore
Mealy
RegisteredOutput

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1.One"State"Process

FSM_FF:
process (CLK, RESET)

begin
if RESET='1' then
STATE <= START ;
elsif CLK'event and CLK='1' then
case STATE is
when START => if X=GO_MID then
STATE <= MIDDLE ;
end if ;
when MIDDLE => if X=GO_STOP then
STATE <= STOP ;
end if ;
when STOP => if X=GO_START then
STATE <= START ;
end if ;
when others => STATE <= START ;
end case ;
end if ;
end process FSM_FF ;

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2.Two"State"Processes

FSM_FF: process (CLK, RESET) begin

if RESET='1' then
STATE <= START ;
elsif CLK'event and CLK='1' then
STATE <= NEXT_STATE ;
end if;
end process FSM_FF ;
FSM_LOGIC: process ( STATE , X)
begin
NEXT_STATE <= STATE ;
case STATE is
when START => if X=GO_MID then
NEXT_STATE <= MIDDLE ;
end if ;
when MIDDLE => ...
when others => NEXT_STATE <= START ;
end case ;
end process FSM_LOGIC ;

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3.HowManyProcesses?

StructureandReadability
Asynchronouscombinatoricsynchronousstoringelements
=>2processes
FSMstateschangewithspecialinputchanges
=>1processmorecomprehensible
GraphicalFSM(withoutoutputequations)resemblesonestateprocess
=>1process

Simulation
Errordetectioneasierwithtwostateprocesses
=>2processes

Synthesis
2stateprocessescanleadtosmallergenericnetlist
andthereforetobettersynthesisresults
=>2processes
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4.StateEncoding

type STATE_TYPE is (START,MIDDLE,STOP ) ;

signal STATE : STATE_TYPE ;

Stateencodingresponsible
forsafetyofFSM

START
-> "00 "
MIDDLE -> "01 "
STOP
-> "10 "

Defaultencoding:binary

START -> "001 "

MIDDLE -> "010 "
STOP
-> "100 "

Speedoptimizeddefault
encoding:onehot

if{ld(#ofstates)ENTIER[ld(#ofstates)]}=>unsafeFSM!
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5.ExtensionofCaseStatement

type STATE_TYPE is (START, MIDDLE, STOP) ;

signal STATE : STATE_TYPE ;

case STATE is
when START =>
when MIDDLE =>
when STOP
=>

Addingthe"whenothers"choice

whenothers=>
end case ;

Notsimulatable;
inRTLthereexistnoothervaluesforSTATE

Notnecessarilysafe;
somesynthesistoolswillignore"whenothers"choice
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6.ExtensionofTypeDeclaration

type STATE_TYPE is (START, MIDDLE, STOP, DUMMY) ;

signal STATE : STATE_TYPE ;

case STATE is
when START =>
when MIDDLE =>
when STOP
=>
whenDUMMY=>

-- or when others

end case ;

{2**(ENTIER[ld(n)])-n}dummystates
(n=20=>12dummystates)

Changingtoonehotcoding=>unnecessaryhardware
(n=20=>12unnecessaryFlipFlops)
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Addingdummyvalues
Advantages:
Nowsimulatable
SafeFSMafter
synthesis

7.HandCoding

subtype STATE_TYPE is std_ulogic_vector (1 downto 0) ;

signal STATE : STATE_TYPE ;
constant START : STATE_TYPE := "01";
constant MIDDLE : STATE_TYPE := "11";
constant STOP : STATE_TYPE := "00";

case STATE is
when START =>
when MIDDLE =>
when STOP
=>
when others
=>
end case ;

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Definingconstants
Controlofencoding
SafeFSM
Simulatable
Portabledesign
Moreeffort

8.FSM:Medvedev

Theoutputvectorresemblesthestatevector:Y=S

TwoProcesses
architecture RTL of MEDVEDEV is
...
begin
REG: process (CLK, RESET)
begin
-- State Registers Inference
end process REG ;

CMB: process (X, STATE)

begin
-- Next State Logic
end process CMB ;

Y <= S ;
end RTL ;

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OneProcess
architecture RTL of MEDVEDEV is
...
begin
REG: process (CLK, RESET)
begin
-- State Registers Inference with Logic Block
end process REG ;

Y <= S ;
end RTL ;

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9.MedvedevExample

architecture RTL of MEDVEDEV_TEST is

signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: process (CLK, RESET)
begin
if RESET=`1` then
STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ;
end if ;
end process REG;

CMB: process (A,B,STATE)

begin
NEXT_STATE <= STATE;
case STATE is
when START => if (A or B)=`0` then
NEXTSTATE <= MIDDLE ;
end if ;
when MIDDLE => if (A and B)=`1` then
NEXTSTATE <= STOP ;
end if ;
when STOP => if (A xor B)=`1` then
NEXTSTATE <= START ;
end if ;
when others => NEXTSTATE <= START ;
end case ;
end process CMB ;
-- concurrent signal assignments for output

(Y,Z) <= STATE ;

end RTL ;

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10.WaveformMedvedevExample

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11.FSM:Moore

Theoutputvectorisafunctionofthestatevector:Y=f(S)
ThreeProcesses

TwoProcesses

architecture RTL of MOORE is

...
begin

architecture RTL of MOORE is

...
begin

REG: -- Clocked Process

CMB: -- Combinational Process

OUTPUT: process (STATE)

begin
-- Output Logic
end process OUTPUT ;
end RTL ;

REG: process (CLK, RESET)

begin
-- State Registers Inference with Next State Logic
end process REG ;

OUTPUT: process (STATE)

begin
-- Output Logic
end process OUTPUT ;
end RTL ;

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4.5.12MooreExample

architecture RTL of MOORE_TEST is

signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: process (CLK, RESET) begin
if RESET=`1` then STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ;
end if ; end process REG ;
CMB: process (A,B,STATE) begin
NEXT_STATE <= STATE;
case STATE is
when START => if (A or B)=`0` then
NEXTSTATE <= MIDDLE ;
end if ;
when MIDDLE => if (A and B)=`1` then
NEXTSTATE <= STOP ;
end if ;
when STOP => if (A xor B)=`1` then
NEXTSTATE <= START ;
end if ;
when others => NEXTSTATE <= START ;
end case ; end process CMB ;
-- concurrent signal assignments for output
Y <= ,1` when STATE=MIDDLE else ,0` ;
Z <= ,1` when STATE=MIDDLE
or STATE=STOP else ,0` ;
end RTL ;

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13.WaveformMooreExample

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14.FSM:Mealy

Theoutputvectorisafunctionofthestatevector
andtheinputvector:Y=f(X,S)

ThreeProcesses
architecture RTL of MEALY is
...
begin
REG: -- Clocked Process
CMB: -- Combinational Process
OUTPUT: process (STATE, X)
begin
-- Output Logic
end process OUTPUT ;
end RTL ;

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TwoProcesses
architecture RTL of MEALY is
...
begin
MED: process (CLK, RESET)
begin
-- State Registers Inference with Next State Logic
end process MED ;
OUTPUT: process (STATE, X)
begin
-- Output Logic
end process OUTPUT ;
end RTL ;

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15.MealyExample

architecture RTL of MEALY_TEST is

signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: -- clocked STATE process
CMB: -- Like Medvedev and Moore Examples
OUTPUT: process (STATE, A, B)
begin
case STATE is
when START =>
Y <= `0` ;
Z <= A and B ;
when MIDLLE =>
Y <= A nor B ;
Z <= '1' ;
when STOP =>
Y <= A nand B ;
Z <= A or B ;
when others =>
Y <= `0` ;
Z <= '0' ;
end case;
end process OUTPUT;
end RTL ;

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16.WaveformMealyExample

(Y,Z)changeswithinput=>Mealymachine
Notethe"spikes"ofYandZinthewaveform
FSMhastobemodeledcarefullyinordertoavoidspikesinnormaloperation.

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17.ModellingAspects

Medvedevistooinflexible
Mooreispreferredbecauseofsafeoperation
Mealymoreflexible,butdangerof
Spikes
Unnecessarylongpaths(maximumclockperiod)
Combinationalfeedbackloops

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1.8RegisteredOutput

Avoidinglongpathsanduncertaintiming
Withoneadditionalclockperiod

Withoutadditionalclockperiod(Mealy)

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19.RegisteredOutputExample(1)

architecture RTL of REG_TEST is

signal Y_I , Z_I : std_ulogic ;
signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: -- clocked STATE process
CMB: -- Like other Examples
OUTPUT: process (STATE, A, B)
begin
case STATE is
when START =>
Y_I<= `0` ;
Z_I<= A and B ;

end process OUTPUT

-- clocked output process
OUTPUT_REG: process(CLK) begin
if CLK'event and CLK='1' then
Y <= Y_I ;
Z <= Z_I ;
end if ;
end process OUTPUT_REG ;
end RTL ;

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20.WaveformRegisteredOutputExample(1)

OneclockperioddelaybetweenSTATEandoutputchanges.
Inputchangeswithclockedgeresultinanoutputchange.
(Dangerofunmeantvalues)

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21.RegisteredOutputExample(2)

architecture RTL of REG_TEST2 is

signal Y_I , Z_I : std_ulogic ;
signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: -- clocked STATE process
CMB: -- Like other Examples
OUTPUT: process ( NEXTSTATE , A, B)
begin
case NEXTSTATE is
when START =>
Y_I<= `0` ;
Z_I<= A and B ;

end process OUTPUT

OUTPUT_REG: process(CLK)
begin
if CLK'event and CLK='1' then
Y <= Y_I ;
Z <= Z_I ;
end if ;
end process OUTPUT_REG ;
end RTL ;

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2.2WaveformRegisteredOutputExample(2)

NodelaybetweenSTATEandoutputchanges.

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