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Lesson 4

Synchronous Design Architectures

October 2005

EE37E Adv. Digital


Electronics

Introduction
In this lesson we will present the methods for the
analysis and design of synchronous systems.
We can classify synchronous systems in three
groups:
Data-intensive and few control (arithmetic circuits,
signal processing modules, etc.)
Control-intensive and few data (i.e Traffic light
controller, vending machine, etc.)
Data and control intensive (processors, ATM
switches, etc.)
We will use the Register-transfer level (RTL) approach.
October 2005

EE37E Adv. Digital


Electronics

Design Considerations
A digital system is viewed as a divided into a data
subsystem (also called data path) and control
subsystem.
The state of the data subsystem consists of the contents
of a set of registers.
The function of the system is performed as a sequence
of register transfers (in one ore more clock cycles).
A register transfer is a transformation performed on a
datum while the datum is transferred from one register to
another.
The sequence of register transfer is controlled by the
control subsystem.
A sequence of register transfers in some cases can be
represented by an execution graph.
October 2005

EE37E Adv. Digital


Electronics

Example of execution graph

Consider the evaluation of a polynomial of degree seven,


that is:

To capture better the order of operations, these expressions


can be described by execution graphs depicted in the
following figures.
October 2005

EE37E Adv. Digital


Electronics

Figure 4.1:

October 2005

EE37E Adv. Digital


Electronics

Graphs in figure 4.1 are sequential execution graphs because only one node
can be active at a time. Figure 4.1a depicts a straight-line (unfolded ) graph,
whereas Figure 4.1b uses a loop. In contrast , the graph of figure 4.2a is a
concurrent execution graph because more than one node can be active at a
time.
In Figure 4.2b a
group of nodes
can begin
execution when
the preceding
group has
finished.

Figure 4.2: CONCURRENT EXECUTION GRAPHS FOR POLYNOMIAL EVALUATION: a)


CONCURRENT; AND b) GROUP- SEQUENTIAL.

October 2005

EE37E Adv. Digital


Electronics

Organization of systems
A system implementing an execution graph must
perform two functions:
Data transformations; and
Control of the data transformations and their
sequencing.

To perform these functions, the system contains


data-transformation units (also called functions
units or data-path units or operators) and control
units.

October 2005

EE37E Adv. Digital


Electronics

Types of systems with respect to


functional units

Nonsharing system

Functional unit for each graph node


Connection among units correspond to the arcs of the execution
graph.
Design structure is straightforward, but the number of modules
might be too large, and their interconnection too complex.

Sharing system
Using modules to perform operations in several nodes of the
graph, but at different instant.
Nodes are scheduled in order to avoid shared unit conflicts.

Unimodule system (extreme sharing, just one module is


used to performs all nodes)
October 2005

EE37E Adv. Digital


Electronics

Types of Control

Figure 4.3: CONTROL STRUCTURES: a) CENTRALIZED; b) DECENTRALIZED;


c) SEMICENTRALIZED.
October 2005

EE37E Adv. Digital


Electronics

Figure 4 illustrates a system with nonsharing


functional units and decentralized control,
obtained from the direct mapping of the
execution graph in figure 4.a.
Each box is a module containing:
an operator (adder and/or multiplier);
storage for operands, results, and any intermediate
variable required by the execution of the operations;
and
a controller to controller the execution of the operation

October 2005

EE37E Adv. Digital


Electronics

Figure 4.4: NON-SHARING DATA/DECENTRALIZED CONTROL


IMPLEMENTATION FOR P7(x).
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EE37E Adv. Digital


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Sharing data subsystem and centralized


control

Figure 4.5: SHARING DATA SUBSYSTEM FOR P7(x).


October 2005

EE37E Adv. Digital


Electronics

Unimodule data subsystem


Figure 4.6 depicts a unimodule whose single
module M performs the operation z a x b + c.
This structure also contains a register array R,
which is used to store operands and
intermediate results.
The register array allows reading two values and
writing one.
The connections between the modules allows
the transfer of two operand from R to M and one
result back from M to R.
October 2005

EE37E Adv. Digital


Electronics

Figure 4.6: UNIMODULE DATA SUBSYSTEM FOR P7(x).


October 2005

EE37E Adv. Digital


Electronics

October 2005

EE37E Adv. Digital


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Organization of RTL Systems

October 2005

EE37E Adv. Digital


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Design of RTL Systems

October 2005

EE37E Adv. Digital


Electronics

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