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FSM ASM Diagramas

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Lecture 8

Finite State Machines

State Diagrams,

State Tables,

Algorithmic State Machine (ASM) Charts,

and VHDL code

ECE 448 FPGA and ASIC Design with VHDL

Required reading

P. Chu, FPGA Prototyping by VHDL Examples

Chapter 5, FSM

S. Brown and Z. Vranesic,

Fundamentals of Digital Logic with VHDL Design

Chapter 8, Synchronous Sequential Circuits

Sections 8.1-8.5

Chapter 8.10, Algorithmic State Machine

(ASM) Charts

ECE 448 FPGA and ASIC Design with VHDL

Datapath

vs.

Controller

Data Inputs

Datapath

(Execution

Unit)

Control Inputs

Control

Signals

Controller

(Control

Unit)

Status

Signals

Data Outputs

Status Outputs

Manipulates and processes data

Performs arithmetic and logic operations, shifting,

and other data-processing tasks

Is composed of registers, gates, multiplexers,

decoders, adders, comparators, ALUs, etc.

Provides all necessary resources and

interconnects among them to perform specified

task

Interprets control signals from the Controller and

generates status signals for the Controller

Controls data movements in the Datapath by

switching multiplexers and enabling or disabling

resources

Example: enable signals for registers

Example: control signals for muxes

Provides signals to activate various processing

tasks in the Datapath

Determines the sequence the operations

performed by Datapath

Follows Some Program or Schedule

ECE 448 FPGA and ASIC Design with VHDL

Controller

Controller can be programmable or non-programmable

Programmable

Has a program counter which points to next instruction

Instructions are held in a RAM or ROM externally

Microprocessor is an example of programmable

controller

Non-Programmable

Once designed, implements the same functionality

Another term is a hardwired state machine or

hardwired instructions

In the following several lectures we will be focusing

on non-programmable controllers.

ECE 448 FPGA and ASIC Design with VHDL

Digital Systems and especially their Controllers can be

described as Finite State Machines (FSMs)

Finite State Machines can be represented using

State Diagrams and State Tables - suitable for

simple digital systems with a relatively few inputs

and outputs

Algorithmic State Machine (ASM) Charts suitable for complex digital systems with a large

number of inputs and outputs

All these descriptions can be easily translated to the

corresponding synthesizable VHDL code

Interface

Pseudocode

Datapath

Block

diagram

VHDL code

ECE 448 FPGA and ASIC Design with VHDL

Controller

Block

diagram

VHDL code

State diagram

or ASM chart

VHDL code

9

Refresher

10

Any Circuit with Memory Is a Finite State

Machine

Even computers can be viewed as huge FSMs

Defining states

Defining transitions between states

Optimization / minimization

Manual Optimization/Minimization Is

Practical for Small FSMs Only

ECE 448 FPGA and ASIC Design with VHDL

11

Moore FSM

Output Is a Function of a Present State Only

Inputs

Next State

function

Next State

clock

reset

Present State

Present State

register

Output

function

ECE 448 FPGA and ASIC Design with VHDL

Outputs

12

Mealy FSM

Output Is a Function of a Present State and Inputs

Inputs

Next State

function

Next State

clock

reset

Present State

Present State

register

Output

function

ECE 448 FPGA and ASIC Design with VHDL

Outputs

13

State Diagrams

14

Moore Machine

transition

condition 1

state 1 /

output 1

transition

condition 2

state 2 /

output 2

15

Mealy Machine

transition condition 1 /

output 1

state 2

state 1

transition condition 2 /

output 2

16

Moore and Mealy FSMs Can Be

Functionally Equivalent

Equivalent Mealy FSM can be derived from

Moore FSM and vice versa

Usually Requires Smaller Number of

States

Smaller circuit area

17

Mealy FSM Computes Outputs as soon as

Inputs Change

Mealy FSM responds one clock cycle sooner

than equivalent Moore FSM

Between Inputs and Outputs

Moore FSM is more likely to have a shorter

critical path

18

Moore FSM that Recognizes Sequence 10

0

1

S0 / 0

reset

Meaning

of states:

S0: No

elements

of the

sequence

observed

0

S1 / 0

0

S1: 1

observed

S2 / 1

S2: 10

observed

19

Mealy FSM that Recognizes Sequence

10

0/0

1/0

S0

reset

Meaning

of states:

1/0

S1

0/1

S0: No

elements

of the

sequence

observed

S1: 1

observed

20

clock

input

Moore

Mealy

S0

S1

S2

S0

S0

S0

S1

S0

S0

S0

21

in VHDL

22

FSMs in VHDL

Finite State Machines Can Be Easily

Described With Processes

Synthesis Tools Understand FSM Description

if Certain Rules Are Followed

State transitions should be described in a process

sensitive to clock and asynchronous reset signals

only

Output function described using rules for

combinational logic, i.e. as concurrent statements

or a process with all inputs in the sensitivity list

23

Moore FSM

process(clock, reset)

Inputs

Next State

function

Next State

clock

reset

Present State

Register

Present State

Output

function

Outputs

concurrent

statements

ECE 448 FPGA and ASIC Design with VHDL

24

Mealy FSM

process(clock, reset)

Inputs

Next State

function

Next State

clock

reset

Present State

Present State

Register

concurrent

statements

ECE 448 FPGA and ASIC Design with VHDL

Output

function

Outputs

25

Moore FSM that Recognizes Sequence 10

0

1

S0 / 0

0

S1 / 0

reset

S2 / 1

26

TYPE state IS (S0, S1, S2);

SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)

BEGIN

IF(reset = 1) THEN

Moore_state <= S0;

ELSIF (clock = 1 AND clockevent) THEN

CASE Moore_state IS

WHEN S0 =>

IF input = 1 THEN

Moore_state <= S1;

ELSE

Moore_state <= S0;

END IF;

ECE 448 FPGA and ASIC Design with VHDL

27

WHEN S1 =>

IF input = 0 THEN

Moore_state <= S2;

ELSE

Moore_state <= S1;

END IF;

WHEN S2 =>

IF input = 0 THEN

Moore_state <= S0;

ELSE

Moore_state <= S1;

END IF;

END CASE;

END IF;

END PROCESS;

Output <= 1 WHEN Moore_state = S2 ELSE 0;

ECE 448 FPGA and ASIC Design with VHDL

28

Mealy FSM that Recognizes Sequence

10

0/0

1/0

S0

reset

1/0

S1

0/1

29

TYPE state IS (S0, S1);

SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)

BEGIN

IF(reset = 1) THEN

Mealy_state <= S0;

ELSIF (clock = 1 AND clockevent) THEN

CASE Mealy_state IS

WHEN S0 =>

IF input = 1 THEN

Mealy_state <= S1;

ELSE

Mealy_state <= S0;

END IF;

ECE 448 FPGA and ASIC Design with VHDL

30

WHEN S1 =>

IF input = 0 THEN

Mealy_state <= S0;

ELSE

Mealy_state <= S1;

END IF;

END CASE;

END IF;

END PROCESS;

Output <= 1 WHEN (Mealy_state = S1 AND input = 0) ELSE 0;

31

Charts

32

Algorithmic State Machine

representation of a Finite State Machine

suitable for FSMs with a larger number of

inputs and outputs compared to FSMs

expressed using state diagrams and state

tables.

33

State name

Output signals

or actions

(Moore type)

0 (False)

Condition

expression

1 (True)

Conditional outputs

or actions (Mealy type)

ECE 448 FPGA and ASIC Design with VHDL

34

State Box

State box represents a state.

Equivalent to a node in a state diagram or a

row in a state table.

Contains register transfer actions or output

signals

Moore-type outputs are listed inside of the

box.

It is customary to write only the name of the

signal that has to be asserted in the given

state, e.g., z instead of z<=1.

Also, it might be useful to write an action to be

taken, e.g., count <= count + 1, and only later

translate it to asserting a control signal that

causes a given action to take place (e.g.,

enable signal of a counter).

ECE 448 FPGA and ASIC Design with VHDL

State name

Output signals

or actions

(Moore type)

35

Decision Box

Decision box

indicates that a

given condition is to

be tested and the

exit path is to be

chosen accordingly

The condition

expression may

include one or more

inputs to the FSM.

ECE 448 FPGA and ASIC Design with VHDL

0 (False)

Condition

expression

1 (True)

36

Conditional

output box

Denotes output

signals that are of

the Mealy type.

The condition that

determines whether

such outputs are

generated is

specified in the

decision box.

Conditional outputs

or actions (Mealy type)

37

Algorithmic state machines can model both

Mealy and Moore Finite State Machines

They can also model machines that are of

the mixed type

38

Reset

w =1

w =0

A z = 0

B z = 0

w =0

w =1

w =0

C z = 1

w =1

39

Next state

Present

state w = 0 w = 1

A

B

C

A

A

A

B

C

C

Output

z

0

0

1

40

Reset

w

1

B

w

1

C

z

41

USE ieee.std_logic_1164.all ;

ENTITY simple IS

PORT ( clock

resetn

w

z

END simple ;

: IN STD_LOGIC ;

: IN STD_LOGIC ;

: IN STD_LOGIC ;

: OUT STD_LOGIC ) ;

TYPE State_type IS (A, B, C) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( resetn, clock )

BEGIN

IF resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

ECE 448 FPGA and ASIC Design with VHDL

42

CASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

WHEN C =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

END CASE ;

ECE 448 FPGA and ASIC Design with VHDL

43

END IF ;

END PROCESS ;

z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;

44

Reset

w = 1 z = 0

w = 0 z = 0

w = 1 z = 1

w = 0 z = 0

45

Reset

w

1

B

z

46

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY Mealy IS

PORT ( clock : IN

resetn : IN

w

: IN

z

: OUT

END Mealy ;

STD_LOGIC ;

STD_LOGIC ;

STD_LOGIC ;

STD_LOGIC ) ;

TYPE State_type IS (A, B) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( resetn, clock )

BEGIN

IF resetn = '0' THEN

y <= A ;

ELSIF (clock'EVENT AND clock = '1') THEN

ECE 448 FPGA and ASIC Design with VHDL

47

CASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

END CASE ;

48

END IF ;

END PROCESS ;

z <= '1' WHEN (y = B) AND (w=1) ELSE '0' ;

END Behavior ;

49

reset

g1

r1

r2

Arbiter

g2

g3

r3

clock

ECE 448 FPGA and ASIC Design with VHDL

50

000

Reset

Idle

0xx

1xx

gnt1g1 =1

x0x

1xx

01x

gnt2g2 =1

xx0

x1x

001

gnt3g3 =1

xx1

ECE 448 FPGA and ASIC Design with VHDL

51

r 1r 2 r 3

Reset

Idle

r1

r1

gnt1 g1 = 1

r1

r2

r 1r 2

gnt2 g2 = 1

r2

r3

r 1r 2 r 3

gnt3 g3 = 1

r3

ECE 448 FPGA and ASIC Design with VHDL

52

Reset

Idle

r1

1

gnt1

1

g1

r2

gnt2

g2

r3

r1

r2

1

1

gnt3

g3

r3

53

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY arbiter IS

PORT ( Clock, Resetn

r

g

END arbiter ;

: IN

: IN

: OUT

STD_LOGIC ;

STD_LOGIC_VECTOR(1 TO 3) ;

STD_LOGIC_VECTOR(1 TO 3) ) ;

TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;

SIGNAL y : State_type ;

54

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN y <= Idle ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS

WHEN Idle =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSIF r(2) = '1' THEN y <= gnt2 ;

ELSIF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt1 =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt2 =>

IF r(2) = '1' THEN y <= gnt2 ;

ELSE y <= Idle ;

END IF ;

ECE 448 FPGA and ASIC Design with VHDL

55

WHEN gnt3 =>

IF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

g(1) <= '1' WHEN y = gnt1 ELSE '0' ;

g(2) <= '1' WHEN y = gnt2 ELSE '0' ;

g(3) <= '1' WHEN y = gnt3 ELSE '0' ;

END Behavior ;

56

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