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Modified Booth Multiplier

Digital Electronics
Fall 2008
Project 2

Booth Multiplier: an Introduction


Recode each 1 in multiplier as +2-1
Converts sequences of 1 to 100(-1)
Might reduce the number of 1s
0

Spring 2006

+1

+1
-1

+1
-1
0

+1
-1

1
+1
-1

+1
-1

-1

-1

EE 5324 - VLSI Design II - Kia


Bazargan

Booth Multiplier: Recoding (Encoding)


Example
0

(+1 -1)
(+1 -1)

(+1 -1)
(+1 -1)
(+1 -1)

+1

+1

-1

-1

(+1

-1)

+1

-1

If you use the last row in multiplication,


you should get exactly the same result
as using the first row (after all, they
represent the same number!)
Spring 2006

EE 5324 - VLSI Design II - Kia


Bazargan

Booth Recoding: Multiplication


Example
Sign extension

1 1

0
0 0
0 0 1
0 0 1
Spring 2006

0
0
1
0

0 0 1
0 1 1
+1 0
0 0 0
1 0 1
0 0 0
0 0
0
1 0 1

1
1
0
0
0

0
6x
0
14
-1 0
0
(-6)

0 0

EE 5324 - VLSI Design II - Kia


Bazargan

84
4

Booth Recoding: Advantages


and Disadvantages
Depends on the architecture
Potential advantage: might reduce the # of 1s
in multiplier

In the multipliers that we have seen so


far:
Doesnt save in speed
(still have to wait for the critical path, e.g., the
shift-add delay in sequential multiplier)
Increases area: recoding circuitry AND
subtraction
Spring 2006

EE 5324 - VLSI Design II - Kia


Bazargan

Modified Booth
Booth 2 modified to produce at most n/2+1
partial products.
Algorithm: (for unsigned numbers)

Pad the LSB with one zero.


Pad the MSB with 2 zeros if n is even and 1 zero
if n is odd.
Divide the multiplier into overlapping groups of
3-bits.
Determine partial product scale factor from
modified booth 2 encoding table.
Compute the Multiplicand Multiples
Sum Partial Products

Modified Booth Multiplier: Idea


(cont.)

Can encode the digits by looking at three


bits at a time
Booth recoding table:
i+1

i-1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Spring 2006

Must be able to add


add
multiplicand times 2,
-1, 0, 1 and 2
0*M Since Booth recoding
1*M
got rid of 3s,
1*M
generating partial
products is not that
2*M
hard (shifting and
2*M
negating)
1*M
1*M
0*M
EE 5324 - VLSI Design II - Kia
Bazargan

[Hauck]
7

Modified Booth
Example: (n=4-bits unsigned)
1.Pad LSB with 1 zero
Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

2.n is even then pad the MSB with two zeros


0

Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

3.Form 3-bit overlapping groups for n=8 we


have 05 groups
0 0 0 0 1 0 1 0 0 0
0

Modified Booth
4. Determine partial product scale factor
from modified booth 2 encoding table.
0

Xi+

Xi

Xi-1

Actio
n

0Y

Codi
ng

1Y

1Y

2Y

-2
Y

-1
Y

-1
Y

Groups
0

0Y

1Y

1Y

0Y

0Y

Modified Booth
5. Compute the Multiplicand Multiples
000001000 1
Codi
ng

Groups

0 0 0 0 1 0 1 0 0 20

0Y

00000000000000000
Y

1Y

00000000001000

1Y

1
Y

0Y

000000001000

0Y

1
Y

0000000000

0
Y

00000000

0
Y

Compute Partial Products


Xi+

Xi

Xi-1

Actio
n

0Y

1Y

1Y

2Y

-2
Y

-1
Y

-1
Y

0Y

Yi-1
Adders
Yi

Xi-1 Xi Xi+1

Modified Booth
6. Sum Partial Products
000001000 1
0 0 0 0 1 0 1 0 0 20
00000000000000000
Y
00000000001000
+0 0 0 0 0 0 0 0 1 0 0 0

1
Y
1
Y

0000000000

0
Y

00000000

0
Y

Modified Booth
Booth 2 modified to produce at most n/2+1
partial products.
Algorithm: (for unsigned numbers)

Pad the LSB with one zero.


If n is even dont pad the MSB ( n/2 PPs) and if n
is odd sign extend the MSB by 1 bit ( n+1/2 PPs).
Divide the multiplier into overlapping groups of 3bits.
Determine partial product scale factor from
modified booth 2 encoding table.
Compute the Multiplicand Multiples
Sum Partial Products

Modified Booth
Example: (n=4-bits unsigned)
1.Pad LSB with 1 zero
Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

2.n is even then do not pad the MSB


Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

Y
7

Y
6

Y
5

Y
4

Y
3

Y
2

Y
1

Y
0

3.Form 3-bit overlapping groups for n=8 we


have 5 groups
0 1 1 0 1 0 0 1 0

Modified Booth
4. Determine partial product scale factor
from modified booth 2 encoding table.
0

Xi+

Xi

Xi-1

Actio
n

0Y

Codi
ng

1Y

1Y

Groups
0

1Y

2Y

-2
Y

-2
Y

-1
Y

-1
Y

2Y

-1
Y

Modified Booth
5. Compute the Multiplicand Multiples
1 0 0 1 0 1 0 1 -107

Groups

01101001

105

Codi
ng

1111111110010101 1Y

1Y

00000011010110

-2 Y

-2
Y

000001101011

-1 Y

0100101010

2Y

1101010000011101

11235

-1
Y

2Y

Modified Booth Multiplier: Idea


(cont.)

Interpretation of the Booth recoding


table:
i+1
i
i-1
add Explanation
0
0
0
0
1
1
1
1
Spring 2006

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0*M No string of 1s in sight


1*M End of a string of 1s
1*M Isolated 1
2*M End of a string of 1s
2*M Beginning of a string of 1s
1*M End one string, begin new o
1*M Beginning of a string of 1s
0*M Continuation of string of 1s
EE 5324 - VLSI Design II - Kia
Bazargan

[Par] p. 160
17

Modified Booth Recoding:


Summary
Grouping multiplier bits into pairs
Orthogonal idea to the Booth recoding
Reduces the num of partial products to half
If Booth recoding not used have to be
able to multiply by 3 (hard: shift+add)

Applying the grouping idea to Booth


Modified Booth Recoding (Encoding)
We already got rid of sequences of 1s
no mult by 3
Just negate, shift once or twice
Spring 2006

EE 5324 - VLSI Design II - Kia


Bazargan

18

Modified Booth Multiplier:


Summary (cont.)
Uses high-radix to reduce number of
intermediate addition operands
Can go higher: radix-8, radix-16
Radix-8 should implement *3, *-3, *4, *-4
Recoding and partial product generation
becomes more complex

Can automatically take care of signed


multiplication
(we will see why)
Spring 2006

EE 5324 - VLSI Design II - Kia


Bazargan

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