Beruflich Dokumente
Kultur Dokumente
ARM7TDMI processor
The ARM7TDMI processor is a member of the Advanced
RISC machine family of general purpose 32-bit
microprocessor
What does mean ARM7TDMI ?
ARM7 - 32-bit Advanced RISC Machine
T - Thumb architecture extension
Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb
instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension
3-stage pipeline
fetch, decode, execute
37 32-bit registers
32x8 Multiplier
Barrel Shifter
Switching state
Entering THUMB state
BX instruction with the state bit (bit 0) set in the operand register.
Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,), if
the exception was entered with the processor in THUMB state.
ARM7TDMI Registers
The ARM7TDMI has a total of 37 registers:
31 general-purpose 32-bit registers
6 status registers
10
Control Bits
The I, F, T and M[4:0]) bits will be changed when an exception arises. If
the processor is operating in a privileged mode, they can also be
manipulated by software.
T bit:
This reflects the operating state. When this bit is set, the processor is
executing in THUMB state, otherwise it is executing in ARM state. This is
reflected on the TBIT external signal.
Note that the software must never change the state of the TBIT in the CPSR.
If this happens, the processor will enter an unpredictable state.
11
Mode bits:
The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These
determine the processor's operating mode. Not all combinations of the
mode bits define a valid processor mode. Only those explicitly described
shall be used. The user should be aware that if any illegal value is
programmed into the mode bits, M[4:0], then the processor will enter an
unrecoverable state. If this occurs, reset should be applied.
12
Exceptions (1/6)
Exceptions arise whenever the normal flow of a program
has to be halted temporarily
For example to service an interrupt from a peripheral.
Exception
Mode in Entry
0x00000000
Reset
Supervisor
0x00000004
Undefined instruction
Undefined
0x00000008
Software Interrupt
Supervisor
0x0000000C
Abort (prefetch)
Abort
0x00000010
Abort (data)
Abort
0x00000014
Reserved
Reserved
0x00000018
IRQ
IRQ
0x0000001C
FIQ
FIQ
13
Exceptions (2/6)
When handling an exception, the ARM7TDMI:
Preserves the address of the next instruction in the appropriate Link
Register
Copies the CPSR into the appropriate SPSR
Forces the CPSR mode bits to a value which depends on the
exception
Forces the PC to fetch the next instruction from the relevant
exception vector
It may also set the interrupt disable flags to prevent otherwise
unmanageable nestings of exceptions.
If the processor is in THUMB state when an exception occurs, it will
automatically switch into ARM state when the PC is loaded with the
exception vector address.
14
Exceptions (3/6)
On completion, the exception handler:
Moves the Link Register, minus an offset where appropriate, to the
PC. (The offset will vary depending on the type of exception.)
Copies the SPSR back to the CPSR
Clears the interrupt disable flags, if they were set on entry
15
Exceptions (4/6)
Reset
When the processors Reset input is asserted
CPSR Supervisor + I + F
PC 0x00000000
Undefined Instruction
If an attempt is made to execute an instruction that is undefined
LR_undef Undefined Instruction Address + #4
PC 0x00000004, CPSR Undefined + I
Return with : MOVS pc, lr
Prefetch Abort
Instruction fetch memory abort, invalid fetched instruction
LR_abt Aborted Instruction Address + #4, SPSR_abt CPSR
PC 0x0000000C, CPSR Abort + I
Return with : SUBS pc, lr, #4
16
Exceptions (5/6)
Data Abort
Data access memory abort, invalid data
LR_abt Aborted Instruction + #8, SPSR_abt CPSR
PC 0x00000010, CPSR Abort + I
Return with : SUBS pc, lr, #4 or SUBS pc, lr, #8
Software Interrupt
Enters Supervisor mode
LR_svc SWI Address + #4, SPSR_svc CPSR
PC 0x00000008, CPSR Supervisor + I
Return with : MOV pc, lr
17
Exceptions (6/6)
Interrupt Request
Externally generated by asserting the processors IRQ input
LR_irq PC - #4, SPSR_irq CPSR
PC 0x00000018, CPSR Interrupt + I
Return with : SUBS pc, lr, #4
18
Summary
20
21
Suffix
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
EQ
NE
CS
CC
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Flags
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C clear or Z set
N equals V
N not equal to V
Z clear AND (N equals V)
Z set OR (N not equal to V)
(ignored)
Meaning
Equal
Not equal
Unsigned higher or same
Unsigned lower
Negative
Positive or zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Greater or equal
Less than
Greater than
Less than or equal
always
22
func
Examples
B
BCC
label
label
BEQ
label
MOV PC, #0
BL
func
MOV PC, LR
MOV LR, PC
LDR PC, =func
24
25
OP Code
AND
EOR
WUB
RSB
ADD
ADC
SBC
RSC
TST
TEQ
CMP
CMN
ORR
MOV
BIC
MVN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Action
Operand1 AND operand2
Operand1 EOR operand2
Operand1 operand2
Operand2 operand1
Operand1 + operand2
Operand1 + operand2 + carry
Operand1 operand2 + carry 1
Operand2 operand1 + carry 1
As AND, but results is not written
As EOR, but result is not written
As SUB, but result is not written
As ADD, but result is not written
Operand1 OR operand2
Operand2 (operand1 is ignored)
Operand1 AND NOT operand2 (Bit clear)
NOT operand2 (operand1 is ignored)
26
R4, R2, R1
R4, R2, R1
R7, R8, R9, R3
UMULL
UMLAL
; R4 = bits 0 to 31 of R2xR3
; R8 = bits 32 to 63 of R2 x R3
; R6, R8 = R0 x R1
; R5, R8 = R0 x R1 + R5, R8
28
pre-increment
post-increment
pre-decrement
post-decrement
31
Summary
33
001
Always
condition
31
1110
10
Major
opcode
28
Minor
opcode
24
00 1
Rd
Constant
Destination &
source register
21 20 19
0100 1
16 15
Rd
Zero extended
constant
12
Rd
11
0000
Constant
I op1+op2 S
ARM: ADDS Rd, Rd, #Constant
35
Branch Instructions
Thumb supports four types of branch instruction:
an unconditional branch that allows a forward or backward branch of
up to 2Kbytes
a conditional branch to allow forward and backward branches of up
to 256 bytes
a branch with link is supported with a pair of instructions that allow
forward and backwards branches of up to 4Mbytes
a branch and exchange instruction branches to an address in a
register and optionally switches to ARM code execution
B
B
BL
BX
conditional branch
unconditional branch
Branch with link
Branch and exchange instruction set
36
MOV, Move
MUL, Multiply
MVN, Move NOT
NEG, Negate
ORR, Logical OR
ROR, Rotate Right
SBC, Subtract with Carry
SUB, Subtract
TST, Test
37
LDR
LDRB
LDRH
LDRSB
LDRSH
STR
STRB
STRH
Load word
Load unsigned byte
Load unsigned halfword
Load signed byte
Load signed halfword
Store word
Store byte
Store halfword
38
LDM
POP
PUSH
STM
Load multiple
Pop multiple
Push multiple
Store multiple
39
ARM vs THUMB
Code size
Generally, routines in THUMB code are between 65 and 70%
the size of the equivalent ARM code.
60%
65%
%ofARMcodesize
70%
75%
41
42
Gives....
Long branch range
Powerful arithmetic operations
Large address space
44