Ece260b w05 Power Intro

ECE260B
CSE241A
Winter 2005
Power Consumption
Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B CSE 241A Power Consumption 1
http://vlsicad.ucsd.edu
VLSI Design Metrics
Area / cost
Performance
Power consumption
Manufacturing yield
Reliability
Signal integrity (e.g., crosstalk, supply voltage drop, etc.)
Logic correctness / acceptable performance variation under

process, operating condition variations
Expected lifetime (due to eletromigration, soft-error, peak current,

etc.)
Figure courtesy, D. Singh
Power Dissipation
Lead Microprocessors power continues to increase
Power (Watts)
100
P6
Pentium proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Power delivery and dissipation will be prohibitive(?)

Courtesy, Intel
Power Density
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
Year
2000
2010
Power density too high to keep junctions at low temp(?)

Courtesy, Intel
Low Power Design Drivers
Consumer products
Affects expected battery lifetime
Slow development of battery technology (90-110 Watt-hrs/Kg)
Low power reducing energy consumption
High performance designs
Increasingly expensive packaging and cooling strategies

- Size, weight, heat sinks,
- Air, liquid cooling mechanism
Supply voltage drop
Temperature
- Every 10OC increase in operating temperature roughly doubles a
components failure rate
Low power reducing peak power consumption for less

thermal effects, better signal integrity and reliability
- Signal integrity / logic correctness / acceptable performance
variation / design lifetime
Low Power Design Metrics
Energy efficiency in Joules
Energy = power * delay (Joules = Watts * seconds)
Affects battery lifetime
Average power consumption in Watts
Results in thermal effects
Sets packaging limits (50W / cm2 ? 120W total ?) ($1/Watt ?)
Worst case supply current
Simultaneous transistor switching
Supply voltage drop performance degradation
Maximum device current device lifetime
Electromigration wire lifetime
Power Versus Energy

Power is height of curve
Watts
Lower power design could simply be slower

Approach 1
Approach 2
Watts
time
Energy is area under curve
Two approaches require the same energy
Approach 1
Approach 2
time
Slide courtesy of Mary Jane Irwin, PSU
Low Power Design Objectives
Worst case supply current I

Average power P = I V
Maximum cycle power
Maximum N-cycle power
Maximum sustainable power
Energy E = P dt
Energy-delay products
Simultaneous power reduction and performance optimization
Usually to reduce average power under timing constraints
Outline
Problem statement
Power dissipation components
Power estimation
Optimization techniques
Static CMOS Gate Power

Power dissipation in static CMOS gate: 3 components
Dynamic capacitive (switching, useful) power
Still dominant component in current technology
Charging and discharging the capacitor
Crowbar current (short-circuit power)
During a transition, current flows through both P and N

transistors simultaneously for a SHORT period of time
Slow transitions worsen short-circuit power
Leakage (useless power) current
Even when a device is nominally OFF (VGS=0), a small amount of

current is still flowing
With many devices, can add up to hundreds of mW

Reducing Dynamic Capacitive (Switching) Power

Capacitance:
Function of fan-out,
wire length,
transistor sizes
Supply Voltage:
Has been dropping
with successive
generations
Pdyn = CL VDD2 P01 f
Activity factor:
How often, on
average, do wires
switch?
Clock frequency:
Increasing
Crowbar (Short-Circuit) Current
Finite slope of the input
signal causes a direct

current path between VDD
and GND for a short period
of time during switching
when both the NMOS and
PMOS transistors are
conducting
When VTN < VIN < VDD+VTP
Transition
time
RP
Both transistors are ON

Current flowing directly from
VDD to VGND is crowbar current
Usually not a problem, e.g.,

P is ON strongly (LIN but with
small VDS if at all)
N is barely ON
Slide courtesy of Ken Yang, UCLA
RN
CL
Leakage (Inactive, Useless) Power
Three sources of leakage

The dominant is the Source-to-Drain leakage current
Even when VGS = 0, a small amount of charge is still present

under the gate
Exponentially related to the gate (and S/D) voltage
ID
Source/Drain are junctions and some amount of reverse

bias, IS is present
W
exp(q (VGS VT ) / nkT )
L
Typically much smaller than S/D leakage
Gate tunneling leakage
When tox is only 5-10atoms, easy for tunneling current to flow
More of an issue sub 0.10-m technology
Slide courtesy of Ken Yang, UCLA
2001 ITRS Projections of 1/and Isd,leak for HP, LP Logic

1.E+01
Isd,leak
High Perf.
1.E+00
1/
High Perf.
1.E-01
1.E-02
1000
1/
Low Pwr
Isd,leak
Low pwr
100
2001 2003 2005 2007 2009 2011 2013 2015
1.E-03
1.E-04
I sd,leak (A/m)
1/ (GHz)
10000
1.E-05
1.E-06
Year
Projections for Low Power Gate Leakage

Simulated Igate, oxy-nitride
1.00
10000
0.90
1000
0.80
100
Tox
0.70
0.60
10
0.50
1
0.1
0.01
0.30
0.20
Oxy-nitride no longer
adequate: high K
needed
0.001
0.0001
2001
0.40
Igate spec.
from ITRS
2002
2003
2004
2005
2006
2007
2010
T ox (normalized)
Jgate (normalized)
100000
0.10
0.00
2013
2016
Year
Need for high K driven by Low Power, not High Performance
Summary: Power and Energy Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage
f01 = P01 * fclock
2 f
P = CL VDD
VDD Ipeak f01 + VLeakage
01 + tsc
DD Ileakage power
Dynamic
power
Short-circuit
(~90% today and
power
(~2% today and
decreasing
(~8% today and
increasing
relatively)
decreasing
relatively)
absolutely)
Designers need to comprehend issues of memory and logic power,

speed/power tradeoffs at the process (HiPerf vs. LowPower) level,
Outline
Problem statement
Power estimation
Design Abstraction Levels

HDL
Behavioral
Synthesis
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Place & Route

Slide courtesy, Prof. J. Rabaey, UCB
Transistor Level Power Estimation

HDL
Behavioral
Synthesis
RTL
Synthesis
Circuit Simulation
Logic
Optimization
Current Flows
Transistor
Optimization
Power Analysis
Place & Route

Power Estimation
Dynamic Analysis
Simulation
requires representative simulation vectors

- Derived by designer
- Automatic (Monte Carlo)
Transitor level (PowerMill)
Very accurate
Much faster than SPICE
Gate level (Powergate, DesignPower)
Faster than transistor level
Still very accurate due to good modeling of power dissipation at

cell-level
Power Ingredients
Dynamic Dissipation
Pdyn = CLVDDVsw f0 1
VDD
In
Out
CL
ISC
Short-Circuit Currents
Psc = VDDIsc
Static Dissipation
Pstat = VDD Ileak
Transistor-Level Power Estimation

I
1
P i (t )v (t )dt
T0
Spice is the reference, but too slow

Commercial tools claim to be within 10% of SPICE
accuracy and up to 1000X faster
Timing Simulation
i(Vdd)
Vdd
in
in
out1
out2
out3
out1
VddVth
out2
out3
Up to 2 orders of magnitude faster than SPICE

Uses simplified (table-lookup) transistor model
Handles leakage, direct path, and reduced swing
Switch-Level Simulation
Up to 3 Orders of Magnitude Faster than Circuit
Accurate for Dynamic Power
Unreliable on leakage and direct path currents
IRSIM
SPICE
Cap (fF/bit)
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
Sample
50
60
Perspective on accuracy and speed
Timing
Switch
Adder
Shift Register
% Error Speedup % Error Speedup
6
15
7
3.7
27
60
4
22
Comparison between circuit simulation (SPICE)

and timing or switch analysis
Transistor Level Power Estimation Tools
PowerMill Epic
Mixed transistor/gate simulation

Piecewise linear model
Star-ADM
Avant!
Mixed analog/digital simulation

Analytic closed-form model
LSIM
Analyst
Mentor
Mixed transistor/gate simulation
Graphics Series-Parallel Switch algorithm

HDL
Behavioral
Synthesis
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Place & Route

Gate-Level Power Estimation

Dynamic
Switching Power (Isw) [70-90%]
Also referred to as capacitive power
Input
Transition
V
IInt
ISW
N
Internal (Short-Circuit) Power (Iint) [10-30%]

Also referred to as short circuit power
ILeak
Ci
GND
Static
Leakage Power (Ileak) [< 1%]
Sub-threshold leakage dominates, some due to leakage substrate
Complete
Completepower
powermodel
modelprovides
providesinfrastructure
infrastructurefor
foranalysis
analysisand
andoptimization
optimization
Gate-Level Power Estimation

toggle rate
state of the gate

input slope
output load
temperature
fabrication process

HDL
Behavioral
Synthesis
RTL
Synthesis
Logic
Optimization
Probabilistic
Analysis
Simulation
with integrated
Power Analysis
Transistor
Optimization
Simulation
Toggle
Rates
Power
Analysis
Place & Route

Simulation Based Power Estimation

Problems:
The relationship of power versus primary input probabilities and activities is a

complicated surface.
The existing methods use discrete points to approximate such a surface.

- The effectiveness strongly depends on the density of the chosen points.
- The more points one chooses, the more accurate results.
- More points directly translate to longer CPU time.
Slide courtesy, Z. Chen, K. Roy
Toggle Rate Estimation
Probabilistic Propagation
no input vectors needed
much faster than simulation
less accurate than simulation
glitches?
Simulation
requires representative simulation vectors

- derived by designer
- automatic (Monte Carlo)
Signal Probability and Activity

Signal probability and activity
Signal probability - probability of a signal being logic ONE
1 T/2
Signal activity (transition density)P
- probability
i(t)dt
i limof signalswitching
T T T / 2
ni(T): the number of switching for i(T) in [-T/2,T/2]
Ai
ni (T)
lim T
T
Power Dissipation in terms of Activity
Normalized activity
f : clock frequency
ai
Ai
f
Normalized power dissipation measure
Approximated power dissipation
Pavg
1 2
Vdd
C jA j
2
jall nodes
Cj : node capacitance Aj : node activity
Normalized power dissipation measure
fanout ( j)a j
jallnodes
fanout(j) : fanout number at node j

Probability Propagation
Let y = f(x1, , xn) be a Boolean function with independent variables xi, the signal probability of f can be obtained in linear time as follows.
where
P ( y ) P ( x1 ) P ( f x1 ) P ( x1 ) P ( f x1 )
are the cofactors of f with respect to x1.
Improve runtime by using a BDD
f x1 f (1, x2 ,..., xn ), f x1 f (0, x2 ,..., xn )
Activity Propagation
Let y = f(x1, , xn) be a Boolean function with independent variables xi, the signal activity of f can be obtained in linear time as follows.
where Boolean difference
where
is the exclusive-or operation.
y
A( y ) P ( ) A( xi )
xi
i 1
n
y
y | x 1 y | x 0
x
Propagate
AND gate
sp(1) = sp1 * sp2
1/2
tp(01) = sp * (1 - sp)
1/2
1/4
7/16
1/2
1/2
Example
1/4
sp = 0.5 * 0.5 = 0.25

tp = 0.25 * (1 - 0.25) = 0.1875
Probability Propagation for Basic Gates
Ignores Temporal and Spatial Correlations

Problem: Reconvergent
Fan-out:
Creates spatial
correlation between
signals
Problems
0.5
0.75
0.5
0.375?
0.5!
P(X) = P(B=1).(P(X=1 | B = 1)
Becomescomplexanduntractablerealfast
Solution to Reconvergence
0.375
Preferred Technique:
Ordered Binary Decision Diagrams
(OBDDs)
Statistics computed in linear time

(but graph size could be
exponential)
Other approaches:
1 0.5
0.75
c
0
0.25
1 0
0
1
a
0.25
0.5
0.125
super-gates
computation of correlation
coefficients
0.375
OBDD
Z = bc + abc
How to introduce time?

And include glitching effects
TOUGH! If one also wants to include spatial effects or be general
Example: Symbolic Simulation Approach (for unit delay)

Symbolic Network
Transition Counters
Value of d at time t=0
Problem: Network can be huge and BDD cannot be created!

Probability Simulation
User specifies typical signal behavior at the circuit inputs using probability waveforms,
which is a sequence of values indicating the probability that the signal is high for a
certain time intervals, and the probability that the signal takes transition from low to high.
0.2
0.6
0.0
0.75
0.5
Propagation is very similar to event driven logic simulation

0.25
0.0
t1
t2
t3
How about sequential circuits?
It
I0
PS0
Next
State
PSt
Comb.
Logic
Next State Logic introduces temporal correlations

between subsequent samples
Either assume that all states have equal probability,

or use statistical Markov chains
Gate-Level Power Estimation Tools

Probabilistic based
Simulation based
DesignPower
Synopsys
PowerSim
Systems Science Simulation based
Power_tool
Veritools
Simulation based
WattWatcher
Gate
Sente
Simulation based
POET
Viewlogic
Simulation based
Xpower
Genashor
Asynchronous designs

HDL
Behavioral
Synthesis
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Place & Route

Power Estimation
Simulation
Monte-Carlo technique
PowerMill at transistor level
Verilog-XL at gate level
Hierarchical simulation
Architectural/gate/transistor-level
Parameterized power model for each module
Statistical estimation
Signal probability propagation
Power Estimation Methodology

RTL library
Synthesis
condition
Synthesis
P&R
RTL planning
/ mapping
Post-layout
netlist
Structure
(macro)
netlist
Power
Characterization
Power model inference &

Estimation code generation
Power
Macro-model
database
Enhanced
RTL
Power model
library generator
Powerlib.vhd
Powerlib.v
RTL design
Testbench
stimuli
RTL
simulation
Powerlib.c
Power
report
Power waveform / profile http://vlsicad.ucsd.edu
Inaccuracies in Power Estimation

In increasing order:
The number of input stimuli did not cause any error above
the 10% mark if we considered at least 10 input patterns
Using a gate-level simulator as opposed to a circuit

simulator caused an error of about +/-15%
Repowering and physical design introduced inaccuracies

below 20%
Glitch power varied between 7%-43%
Optimization and technology mapping may cause power

estimates to be off by an order of magnitude
Internal gate capacitances, which are a function of the

target library, accounted for about half the power
Potential for Power Savings
Power and Synthesis Flow
400%
Behavioral
RTL
50%
Gate
20%
10%
Switch
Accuracy of Power Estimation

Expectations
Algorithmic
Algorithm selection
orders of magnitude
Behavioral
Concurrency
Memory
several times
Power manage
Clock ctrl
10-90%
RT Level
Structural transform.
10-15%
Tech. indep.
Extr/decomp
15%
Tech dep.
Tech. mapping
Gate sizing
20%
20%
Layout
Placement
20%
Power Estimation / Improving Guidelines
Before technology mapping, the accuracy levels are

unacceptable
It is necessary to take into account internal gate

capacitances as well as wire capacitances
Gate-level estimation implies >15% error
Power improving transformations should be
Simulation with as few as 10 patterns from typical inputs for

a typical starting state is often sufficient to reach
confidence levels matching those of gate-level simulation
run in late design stages, they should be
applied only if they can predict significant power improvement, and

should be
applied many times (hundreds) to maximize the confidence of

positively impacting the design
Outline
Problem statement
Power estimation
Low Power Design Techniques
Reducing chip and package capacitance

Scaling the supply / threshold voltages
Using power management strategies
Employing better design techniques
Reducing Capacitance
Minimum area minimum power consumption

Wirelength minimization with switching activities as
weighting factors
Placement / routing / partition / floorplanning
Clock gating
Sleep transistors
CMOS Device and Voltage Scaling
Dual transistor threshold
High Vth transistors optimize performance
Low Vth transistors reduce leakage power
Transistors with the same Vth need to group together
Dual supply voltage
High Vdd transistors on critical paths
Low Vdd transistors reduce power
Level-converters between signals of different voltage swings
Routing cost of dual power supply
Extension of classical transistor sizing algorithm, e.g.,

TILOS
Power Management Strategies
Inactive hardware modules are automatically turned off to

save power (for example, monitors, laptops, etc.)
Transistors on non-critical data paths are slowed down,

e.g., by dynamically scaling down their supply voltages
(for example, in Transmeta microprocessors)
Sleep transistors
Power gating (controllable power supply mechanism)

HDL
Behavioral
Synthesis
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Place & Route

Transistor-Level Power Optimization
Optimizes up to 30,000 transistors at a time
Optimization modes:
Starts from three initial solutions: initial

sizes, all transistors sized up with constant
factor, and all transistor identical size
individual transistor sizing

retain ratios between connected NMOS and
PMOS devices
pseudo-NMOS
Optimization Goals
Delay
Power
Slack
AMPS - Epic

HDL
Behavioral
Synthesis
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Place & Route

Gate-Level Power Optimization

Logic
Logic or
or
Gate
Gate Netlist
Netlist
Switching
Switching Activity
Activity
Constraints
Constraints
(timing,
(timing, power,
power, area)
area)
Logic Optimization
Tech
Library
Power
Power Optimization
Optimization
Parasitics
Parasitics
(Capacitance)
(Capacitance)
Power
Power Optimized
Optimized
Gate
Gate Level
Level Netlist
Netlist
Gate-Level Tradeoffs for Power
Factoring
Structuring
Buffer insertion/deletion
Dont care optimization
Technology mapping
Sizing
Pin assignment
Factoring
Idea: Remove common expressions to reduce capacitance
Pa = 0.1
Pb = 0.5
Pc = 0.5
Caveat: This may increase activity!
Logic Restructuring
Logic restructuring to minimize spurious transitions
Buffer insertion for path balancing

Technology Mapping
a
b
c
d
slack=1
Smaller gates reduce capacitance, but are slower
Technology Mapping
Example: 6-input AND
Implemented using 6 input NAND, 3 input NAND, and 2-input NAND [Bellaouar, ElMasry]
Library 1: High-Speed
Library 2: Low-Area
Technology Mapping Example
Area
Area
Delay
Delay (ns)
(ns)
Energy
Energy (fF)
(fF)
6-input
6-input
99
1.1
1.1
6.7
6.7
3-input
3-input
11
11
0.86
0.86
42.5
42.5
2-input
2-input
13
13
0.83
0.83
89.4
89.4
Mapping results for high speed-library
Library
Library 11
Library
Library 22
6-input
6-input
6.7
6.7
3.5
3.5
3-input
3-input
42.5
42.5
19.5
19.5
2-input
2-input
89.4
89.4
43.7
43.7
Energy comparison between libraries

Sequential Logic Optimization
State encoding
Data encoding in data paths
e.g. use of sign-magnitude , one-hot, or redundant representations
mostly ad hoc
Retiming for low power
seems to be of minimal impact in general
registers can be strategically placed to reduce glitching, or to perform path

balancing
Clock gating
Pre-computation
Clock gating
Requires careful skew control ...

Scary in current logic synthesis world!
Pre-computation
Inputs xi xn are not applied

if pre-computing holds
Other options:
guarded evaluation
set output directly
Power Compiler
Results:
design dependent
library dependent
average 15-20% pushbutton reduction in

power
Low Power Synthesis
Introduce more concurrency for performance improvement
Reduce power consumption by scaling down voltages
Linear power consumption increase
Quadratic power consumption decrease
Concurrency increasing transformations
Loop unrolling
Control flow optimizations
Critical path reducing transformations
Logic level minimization
Retiming
Pipelining
Summary
Design Flow for Power well covered at circuit and gate level
Most emphasis on analysis not much on optimization
Overall optimization results are mixed
Plenty of room at the physical end
transistor sizing, circuit style selection, synthesis for pass-transistor

networks, threshold selection

Ece260b w05 Power Intro

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ECE260B

ECE 260B CSE 241A Power Consumption 1

VLSI Design Metrics

Logic correctness / acceptable performance variation under

Expected lifetime (due to eletromigration, soft-error, peak current,

ECE 260B CSE 241A Power Consumption 2

Figure courtesy, D. Singh

Power delivery and dissipation will be prohibitive(?)

Power Density (W/cm2)

Power density too high to keep junctions at low temp(?)

Low Power Design Drivers

Affects expected battery lifetime

Slow development of battery technology (90-110 Watt-hrs/Kg)

Low power reducing energy consumption

High performance designs

Increasingly expensive packaging and cooling strategies

Supply voltage drop

Low power reducing peak power consumption for less

ECE 260B CSE 241A Power Consumption 5

Low Power Design Metrics

Energy efficiency in Joules

Energy = power * delay (Joules = Watts * seconds)

Affects battery lifetime

Average power consumption in Watts

Results in thermal effects

Sets packaging limits (50W / cm2 ? 120W total ?) ($1/Watt ?)

Worst case supply current

Simultaneous transistor switching

Supply voltage drop performance degradation

Maximum device current device lifetime

Electromigration wire lifetime

ECE 260B CSE 241A Power Consumption 6

Power Versus Energy

Lower power design could simply be slower

ECE 260B CSE 241A Power Consumption 7

Slide courtesy of Mary Jane Irwin, PSU

Low Power Design Objectives

Worst case supply current I

Maximum cycle power

Maximum N-cycle power

Maximum sustainable power

Simultaneous power reduction and performance optimization

Usually to reduce average power under timing constraints

ECE 260B CSE 241A Power Consumption 8

ECE 260B CSE 241A Power Consumption 9

Static CMOS Gate Power

Dynamic capacitive (switching, useful) power

Still dominant component in current technology

Charging and discharging the capacitor

Crowbar current (short-circuit power)

During a transition, current flows through both P and N

Slow transitions worsen short-circuit power

Leakage (useless power) current

Even when a device is nominally OFF (VGS=0), a small amount of

With many devices, can add up to hundreds of mW

ECE 260B CSE 241A Power Consumption 10

Reducing Dynamic Capacitive (Switching) Power

Pdyn = CL VDD2 P01 f

ECE 260B CSE 241A Power Consumption 11

Crowbar (Short-Circuit) Current

Finite slope of the input

signal causes a direct

When VTN < VIN < VDD+VTP

Both transistors are ON