IT 212

Computer
Systems
Organizati
with
Assembly
onLanguage
R a l p h Vo l t a i r e D a y o t
Instructor

What is a

Computer
System?

A computer is an
electronic
device

It operates under the

control of instructions
stored in its own memory

It can accept data

(input)

It can manipulate
data (process)

It can produce
information (output)

A computer is an electronic
device, operating under the
control of instructions stored in its
own memory unit, that can
accept data, manipulate data,
and produce information from the
processing.

It is a complete,
workingcomputer.

Computer systems will

include the computer along
with
anysoftwareandperipheral
devicesthat are necessary
to make the computer
function.

Each computer connected to

the system
canoperateindependently,
but has theability to
communicate with other
externaldevicesand
computers.

The basic functional

units of computer are
made of electronics
circuit and it works with
electrical signal (analog
and digital).

We provide input to the

computer in form of
electrical signal and get
the output in form of
electrical signal.

All the functionalities of

computer can be captured
with 0 and 1 and its
theoretical background
corresponds to two
valued boolean algebra.

The smallest unit of

information that is
represented in computer is
known as Bit ( Binary Digit ),
which is either 0 or 1. Four
bits together is known
asNibble, and Eight bits
together is known asByte.

What is

Computer
Organization?

Computer organization
refers to the operational
units and their
interconnections that
realize the architectural
specifications.

Examples of organizational
attributes include those
hardware details transparent
to the programmer, such as

control signals, interfaces

between the computer
and peripherals, and the
memory technology used.

Central
Processi
ng Unit
(CPU)

Buses

Input
&
Outpu
t
Device
s

Memo
ry

Central
Processing
Unit

The central processor (CPU)

is the chip which acts as a
control center for all
operations. It executes
instructions (a program)
which are contained in the
memory section.

Basic Operations
the transfer of data between itself and
the memory section
manipulation of data in the memory
section or stored internally
the transfer of data between itself and
input/output devices

The CPU is said to be the

brains of any computer
system.
It provides all the timing and
control signals necessary to
transfer data from one point
to another in the system

Von Neumann
Architecture

Named after the

mathematician and
early computer
scientist John von

Neumann

Von Neumann
Architecture

Allows instructions
and data to be mixed
and stored in the same
memory module.

Von Neumann
Architecture

Von Neumann
machines have shared
signals and memory
for code and data.
Thus, the program can
be easily modified by
itself since it is stored
in read-write memory.

Von Neumann
Architecture

Instructions in memory
are executed
sequentially unless a
program instruction
explicitly changes the
order

Harvard
Architecture

A computer
architecture with
physically separate
storage and signal
pathways for
instructions and data.

Harvard
Architecture
The term originated from the
Harvard Mark I relay-based
computer, which stored
instructions on punched tape
(24 bits wide) and data in
electro-mechanical counters
(23 digits wide).

Harvard
Architecture
In a computer using the
Harvard architecture, the
CPU can read both an
instruction and perform a
data memory access at the
same time, even without a
cache.

Harvard
Architecture

Uses separate memory

modules for
instructions and for
data.
It is easier to pipeline
and there are no
memory alignment

SYSTEM BUS

All the components of a

computer are
connected by cables

System Bus

A bus is a set of wires,

that interconnects all
the components
(subsystems) of a
computer

System Bus

A communication
pathway connecting
two or more devices

System Bus

Connects theCPUtomain
memoryon the
motherboard.

System Bus

I/Obuses, which connect

the CPU with the systems
other components, branch
off of the system bus.

System Bus

Bus Speed
The speed of the bus
reflects how many bits of
information can be sent
across each wire each
second.

System Bus

Bus Speed
This would be analogous
to how fast the cars are
driving on our analogical
highway.

System Bus

Bus Speed
Most buses transmit one
bit of data per line, per
clock cycle, although
newer high-performance
buses like AGP may
actually move two bits of
data per clock cycle,
doubling performance.

System Bus

What do buses look like?

System Bus

System Bus

DATA BUS
A collection of wires
through which data is
transmitted from one
part of a computer to
another.

System Bus

DATA BUS
Can be thought of as a
highway on which data
travels within a
computer.

System Bus

DATA BUS
This bus connects all
the computer
components to the CPU
and main memory.

System Bus

DATA BUS
Remember that there is no
difference between data
and instruction at this
level

System Bus

ADDRESS
A collection of wires
used to identify
particular location in
main memory.

System Bus

BUS

ADDRESS

BUS

Identify the source or

destination of data

System Bus

ADDRESS
e.g. CPU needs to
read an instruction
(data) from a given
location in memory

System Bus

BUS

ADDRESS
The information used
to describe the
memory locations
travels along the
address bus.

System Bus

BUS

CONTROL
The connections that
carry control
information between
the CPU and other
devices within the
computer

System Bus

BUS

CONTROL
The control bus
carries signals that
report the status of
various devices.

System Bus

BUS

CONTROL
Control and timing
information

System Bus

BUS

Bus

TRANSACTIONS

System Bus

Bus

TRANSACTIONS

System Bus

Bus

TRANSACTIONS

System Bus

BUS

PROTOCOLS

The set of rules

agreed upon by both
the bus master and
the bus slave as to
how data is to be
transferred over the
bus.
System Bus

BUS

PROTOCOLS

It is used to regulate
the flow of information
between the devices.

System Bus

BUS

PROTOCOLS

Flow control is the

ability of the receiving
device to regulate the
flow of data from the
sending device.

System Bus

BUS

PROTOCOLS

With a synchronous
protocol , data transfers
occur in relation to
successive edges of the
system clock.

SYNCHRONOUS

System Bus

BUS

PROTOCOLS

Inherent in this type of

protocol is the assumption
that data will arrive within
a certain time window. (if
it does not, then the data
is lost.)

SYNCHRONOUS

System Bus

BUS

PROTOCOLS

Asynchronous bus
transfers bear no
particular timing relation
to the system clock;
transfer can take place at
any time

ASYNCHRONOUS

System Bus

BUS

PROTOCOLS

Additional handshake
lines are required in order
to guarantee data
transfers between master
and slave.

ASYNCHRONOUS

System Bus

BUS

PROTOCOLS

Synchronous bus transfer,

by the way of contrast,
only depend on the
system clock (the protocol
being built into the
system).

ASYNCHRONOUS

System Bus

BUS

PROTOCOLS

Asynchronous buses are

useful when matching
the different speeds of
the CPU and peripheral
chips.
ASYNCHRONOUS

System Bus

BUS

PROTOCOLS

A compromise the two

previous bus protocols is
found in the semisynchronous bus, which
approaches the speed of
synchronous buses, but
allows for interfacing to
Semi
- SYNCHRONOUS
peripheral
devices of varying
speeds.

System Bus

BUS

PROTOCOLS

The semi-synchronous bus

operates essentially as an
asynchronous bus until the
peripheral devices is ready to
transfer, after which the bus
becomes synchronous for the
duration of the transfer

Semi - SYNCHRONOUS

System Bus

MEMORY

Memory contains data

or instructions for the
processor to execute

Memory

A device used to store

information for use in a
computer.

Memory

Memory

Memory

Memory

Memory

Memory

Memory

Access Methods
Sequential
Start at the beginning and read through
in order
Access time depends on location of data
and previous location
e.g. tape

Memory

Access Methods
Direct
Individual blocks have unique address
Access is by jumping to vicinity plus
sequential search
Access time depends on location and
previous location
e.g. disk

Memory

Access Methods
Random
Individual addresses identify
locations exactly
Access time is independent of
location or previous access
e.g. RAM

Memory

Access Methods
Associative
Data is located by a comparison with
contents of a portion of the store
Access time is independent of location
or previous access
e.g. cache

Memory

Address Locations
These are sequential number
of locations inside the
memory, each of which are a
specific number of bits wide.

Memory

Address Locations
The more number of
bits per location affects
the speed at which data
can be moved from one
location to another in a
computer system.

Memory

Address Locations
In general, the more bits
per location the faster data
can be transferred.
Each memory location is
referred to as an address,
and generally expressed in
hexadecimal notation
(using base 16 numbers).

Memory

Address Locations
The processor selects a
specific address in
memory by placing the
address on the address
bus .

Memory

Address Locations
The total number of
address locations which
can be accessed by the
processor is known as its

physical address space.

Memory

Access Time
This refers to how long
it takes the processor
to read or write to a
specific memory
location within a chip.

Memory

Volatility

This refers to whether

or not the contents of
the memory is lost
when power is turned
off.

Memory

Volatility

Memory

Random Access Memory

A type ofcomputer
memorythat can
beaccessed randomly;
that is, anybyteof
memory can be
accessed without
touching the preceding
bytes.

Memory

Random Access Memory

RAM is the most

common type of
memory found
incomputersand
otherdevices, such
asprinters.

Memory

Random Access Memory

It loses its data once

the power is
removed, so it is a
volatile memory

Memory

Dynamic RAM (DRAM)

A type
ofphysicalmemoryused in
mostpersonal computers.
The termdynamicindicates
that the memory must be
constantly
refreshed(reenergized) or it
will lose its contents.

Memory

Static RAM (SRAM)

SRAM is a type ofmemorythat
is faster and more reliable
than the more
commonDRAM(dynamic RAM).
The termstaticis derived from
the fact that it doesn't need to
berefreshedlike dynamic
RAM.

Memory

DRAM vs SRAM
DRAM

SRAM

Access Time: 60
nanoseconds
Long cycle time
Needs to be
refreshed
(reenergized)
Cheap

Access Time: 10
nanoseconds
Short cycle time

Memory

No refreshing
needed
Expensive

Register

A register is one of a
small set of data
holding places that
are part of a
computerprocessor.

Memory

Register

A register may hold a

computerinstruction,
a storage address, or
any kind of data (such
as a bit sequence or
individual characters).

Memory

Register
Some instructions specify
registers as part of the
instruction.
For example, an instruction
may specify that the contents
of two defined registers be
added together and then
placed in a specified register.

Memory

Cache
A special highspeedstoragemechanism.
It can be either a reserved
section ofmain memory or
an independent highspeedstorage device.

Memory

Cache
Fast and small compared to
main memory; acts as a
buffer between the CPU and
main memory: it contains the
most recent used memory
locations (address and
contents are recorded here)

Memory

Cache
Logical cache (virtual cache)
stores data using virtual
addresses

Memory

Cache
Physical cache stores data
using main memory physical
addresses

Memory

Cache
Every address reference goes
first to the cache; if the desired
address is found there, then it
is called a cache hit

A cache miss occurs when

the address is not found.

Memory

Cache

Memory

Operation

Cache

Memory

Operation

Cache

Temporal localityrefers
to the reuse of specific
data, and/or resources,
within a relatively small
time duration.

Memory

Cache
Most software exhibits
temporal locality of
access, meaning that it
is likely that same
address will be used
again soon

Memory

Cache

Spatial locality

refers to the use of

data elements within
relatively close storage
locations.

Memory

Cache

Memory

Memory
You turn the computer on.
The computer loads data fromread-only memory(ROM) and performs apower-on selftest(POST) to make sure all the major components are functioning properly. As part of this test,
thememory controller checks all of the memory addresses with a quickread/writeoperation to
ensure that there are no errors in the memory chips. Read/write means that data is written to
abitand then read from that bit.
The computer loads thebasic input/output system(BIOS) from ROM. The BIOS provides the
most basic information about storage devices, boot sequence, security,Plug and Play(auto
device recognition) capability and a few other items.
The computer loads theoperating system(OS) from the hard drive into the system's RAM.
Generally, the critical parts of theoperating systemare maintained in RAM as long as the
computer is on. This allows the CPU to have immediate access to the operating system, which
enhances the performance and functionality of the overall system.
When you open anapplication, it is loaded intoRAM. To conserve RAM usage, many applications
load only the essential parts of the program initially and then load other pieces as needed.
After an application is loaded, anyfilesthat are opened for use in that application are loaded into
RAM.
When yousavea file andclosethe application, the file is written to the specified storage device,
and then it and the application are purged from RAM.

Memory

INPUT/OUTPUT

Is any operation, program,

or device that transfers
data to or from a
computer.

INPUT/OUTPUT

Thisis the communication

between aninformation
processing system, such as
acomputer, and the outside
world, possibly a human or
another information
processing system.

INPUT/OUTPUT

Inputsare the signals or

data received by the system.

Outputs are the signals

ordata/informationsent
from it.

INPUT/OUTPUT

Humans use I/O devices

(or other system) to
communicate with a
computer.

INPUT/OUTPUT

Peripheral devices
allow input and
output to occur.

INPUT/OUTPUT

INPUT/OUTPUT

INPUT/OUTPUT

INPUT/OUTPUT

INPUT/OUTPUT

The basic operation cycle

of a computer

Instruction cycle
INPUT/OUTPUT

It is the process by which a

computer retrieves
aprograminstructionfrom
itsmemory, determines what
actions the instruction requires,
and carries out those actions.

Instruction cycle
INPUT/OUTPUT

This cycle is repeated

continuously by thecentral
processing unit(CPU),
fromboot up to when the
computer is shut down.

Instruction cycle
INPUT/OUTPUT

FETCH
DECOD
E
EXECU
TE
Instruction cycle
INPUT/OUTPUT

In the first phase, the

processor generates the
necessary timing signals to
fetch the next instruction
from the memory system.

Instruction cycle -

FETCH
INPUT/OUTPUT

The instruction is
transferred from memory
to an internal location
inside the processor (the
instruction register)

Instruction cycle -

FETCH
INPUT/OUTPUT

The memory places the

instruction on the Data
Bus, and the processor
then copies the instruction
from the Data Bus to the
Instruction Register.

Instruction cycle -

FETCH
INPUT/OUTPUT

During this phase the

processor (if required by
the instruction) will get
any operand(s) required
by the instruction.

Instruction cycle -

DECODE
INPUT/OUTPUT

The processor transfers the

instruction from the
instruction register to the
Decode Unit.

Instruction cycle -

DECODE
INPUT/OUTPUT

It compares the instruction

to an internal table, and
when a match is found, the
table contains the list of
macro instructions (a number
of steps) which are required
to perform the instruction.

Instruction cycle -

DECODE
INPUT/OUTPUT

During this phase, the

processor executes the
instruction.
Instruction cycle -

EXECUTE
INPUT/OUTPUT

The final part of execute

phase is to adjust the
Instruction Counter to
point to the next
instruction to be executed

Instruction cycle -

EXECUTE
INPUT/OUTPUT

A delay experienced by a
computer processor when
accessing external
memory or another device
that is slow to respond.
WAIT STATES
INPUT/OUTPUT

A program or process in a
wait state is inactive for the
duration of the wait state.

WAIT STATES
INPUT/OUTPUT

For example, an application

program that communicated with
one other program might send
that program a message and
then go into a wait state until it
was "reawakened" by a message
back from the other program.

WAIT STATES
INPUT/OUTPUT

When a computer processor works at

a fasterclock speed(expressed
inMHzor millions of cycles per
second) than the random access
memory (RAM) that sends it
instructions, it is set to go into a wait
state for one or more clock cycles so
that it is synchronized with RAM
speed.

WAIT STATES
INPUT/OUTPUT

In general, the more time a

processor spends in wait
states, the slower the
performanceof that
processor.

WAIT STATES
INPUT/OUTPUT

I/O devices are much

slower than CPU and
memory, thus they can
have timing problems
when interacting with CPU
WAIT STATES
INPUT/OUTPUT

Most CPUs have a control

input signal called READY
(or similar) to deal with
this problem
WAIT STATES
INPUT/OUTPUT

Normally the READY input is high;

when the CPU outputs the
address of the I/O device and sets
the proper control signals,
enabling the three-state buffers
of the I/O device interface, the I/O
device sets READY signal to low

WAIT STATES
INPUT/OUTPUT

CPU will read this signal and

continue to keep the I/O
device addressed until the I/O
device will set READY back
high again; the CPU reads the
data from the bus and
continues its normal operation

WAIT STATES
INPUT/OUTPUT

These are used so the CPU

can perform useful work
while waiting for much
slower devices.

HARDWARE
INTERRUPTS
INPUT/OUTPUT

It is a signal to the
processor emitted
byhardwareor software
indicating an event that
needs immediate
attention.
HARDWARE
INTERRUPTS
INPUT/OUTPUT

An interrupt alerts the

processor to a high-priority
condition requiring the
interruption of the current
code the processor is
executing.
HARDWARE
INTERRUPTS
INPUT/OUTPUT

The CPU may output a

request to an I/O device and
instead polling the device or
entering a wait state, the
CPU then continues
executing instructions,
performing useful work.

HARDWARE
INTERRUPTS
INPUT/OUTPUT

When the I/O device is

ready to transfer data, it
sends an interrupt
request to the CPU, via a
dedicated signal on the
control bus.
HARDWARE
INTERRUPTS
INPUT/OUTPUT

The CPU acknowledges the

interrupt, by asserting an
interrupt acknowledge
signal and reads the data
(or perform whatever
action is required).
HARDWARE
INTERRUPTS
INPUT/OUTPUT

Sequence of events, when an

interrupt occurs:
Do nothing until the current
instruction has been executed
Identify the interrupt and get the
interrupt handler address
Invoke the handler routing (very much
like a normal routing execution)

HARDWARE
INTERRUPTS
INPUT/OUTPUT

The Arithmetic
Logic Unit performs
arithmetic
calculations

Arithmetic Logic Unit

An ALU is a digital circuit

used to perform
arithmetic and logic
operations.

Arithmetic Logic Unit

Typical operations
performed by the ALU
are: add, subtract,
negate, divide, multiply,
shift/rotate, etc.

Arithmetic Logic Unit

ALU normally works

on two numbers at a
time.

Arithmetic Logic Unit

The inputs to the ALU are the

data to be operated on
(calledoperands) and a code
from thecontrol unitindicating
which operation to perform.
Its output is the result of the
computation.

Arithmetic Logic Unit

Often, one of the

numbers is found in an
internal location of the
processor, whilst the
other is a constant or
found in the memory
system.
Arithmetic Logic Unit

The reason for most

arithmetic and logic
operations using
operand's which are
located inside the
processor is speed.
Arithmetic Logic Unit

This is due to not having to

perform a fetch cycle for
transferring the operand
from the memory system to
an internal hold point
(called latch) in order to
execute the instruction.

Arithmetic Logic Unit

A register in a computer
processor that contains
the address (location) of
the instruction being
executed at the current
time.
Program Counter

As each instruction gets

fetched, theprogram
counterincreases its
stored value by 1.

Program Counter

During the fetch cycle,

the processor places the
contents of this counter
on the address bus.

Program Counter

A read signal is issued on the

control bus, then timing signals
are generated to transfer
(copy) the instruction from the
memory location in system
memory to an internal hold
latch inside the processor
(called the instruction register).

Program Counter

During the decode cycle, the

instruction counter is adjusted to
point to the next instruction to
be executed from system
memory (calculated from the
current instruction).

Program Counter

It is the part of a CPU's

control unit that stores
theinstructioncurrently
being executed or
decoded.

Instruction Register

In simple processors each

instruction to be executed
is loaded into the
instruction register which
holds it while it is decoded,
prepared and ultimately
executed.
Instruction Register

Some of the complicated

processors use apipeline
of instruction
registerswhere each stage
of the pipeline does part of
the decoding, preparation
or execution and then
passes it to the next stage
for its step.
Instruction Register

Modern processors can

even do some of the steps
out of order as decoding
on several instructions is
done in parallel.

Instruction Register

References
http://nptel.ac.in/courses/Webcoursecontents/IIT%20Guwahati/comp_org_arc/web/
Computer Systems Organization &
Architecture, John D. Carpinelli, ISBN: 0201-61253-4
Operating Systems A modern
perspective, Garry Nutt, ISBN 0-80531295-1
World Wide Web