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ELEN 468

Advanced Logic Design


Lecture 14
Synthesis of Sequential Logic

ELEN 468 Lecture 14

Synthesis of Sequential Logic:


General
Event control of a cyclic behavior
must be synchronized to a single
edge of a single clock
always @ ( posedge clock )

Different behaviors may be


synchronized to

different clocks
or different edges of a clock
but clock periods should be same
ELEN 468 Lecture 14

Options for Implementing


Sequential Logic
User-defined primitive
Behavior with timing controls
Instantiated library register cell
Instantiated module

ELEN 468 Lecture 14

Commonly Synthesized
Sequential Logic
Data register
Transparent latch
Shift register
Binary counter
Finite state machine
Pulse generator
Clock generator
Parallel/serial converter

Table 9.2, page 346


ELEN 468 Lecture 14

Synthesis of Sequential
UDPs
Only one synchronizing signal

Clock level latch


Clock signal edge flip-flop

A synthesis tool may have its own


requirement

For example, may constrain the order


of rows asynchronous first
ELEN 468 Lecture 14

Example of Sequential
UDP
primitive d_flop( q, clock, d );
clock
output
q;
input
clock, d;
d
q
d_flop
reg q;
table
// clock d
state q/next_state
(01) 0
: ?
:
0;
// Parentheses indicate signal
transition
(01) 1
: ?
:
1;
// Rising clock edge
(0?) 1
: 1
: 1;
(0?) 0
: 0
: 0;
(?0) ?
:
?
:
-;
// Falling clock edge
?
(??) :
?
:
-;
// Steady clock
endtable
endprimitive

ELEN 468 Lecture 14

Synthesis of Latches
Latches are incurred at

Incompletely specified input


conditions for
Continuous assignment -> mux with

feedback
Edge-triggered cyclic behavior -> gated
datapath
Level-sensitive cyclic behavior -> latch

Feedback loop
ELEN 468 Lecture 14

Latch Resulted from


Unspecified Input State
module
modulemyMux(
myMux(y,
y,selA,
selA,selB,
selB,a,
a,
bb););
input
inputselA,
selA,selB,
selB,a,
a,b;
b;
output
outputy;
y;
reg
regy;
y;
always
always@
@((selA
selAor
orselB
selBor
oraaor
or
bb))
case
case(({selA,
{selA,selB}
selB}))
2b10:
2b10:yy==a;
a;
2b01:
2b01:yy==b;
b;
endcase
endcase
endmodule
endmodule

b
selA
selB
selA
selB

en

latch

ELEN 468 Lecture 14

Latch Resulted from Feedback


Loop
module
modulelatch1
latch1((out,
out,in,
in,enable
enable
););
input
inputin,
in,enable,
enable,
output
outputout;
out;
reg
regout;
out;

enabl
e
in

mux

out

always
always@
@((enable
enable))
begin
begin
ifif((enable
enable))
assign
assignout
out==in;
in;
else
else
assign
assignout
out==out;
out;
end
end
endmodule
endmodule

ELEN 468 Lecture 14

Synthesis of Edge-triggered Flipflops


A register variable in a behavior
might be synthesized as a flip-flop if

It is referenced outside the scope of the


behavior
Referenced within the behavior before
it is assigned value
Assigned value in only some branches
of the activity
ELEN 468 Lecture 14

10

Event Control Sensitive to


Multiple Signal Edges
module
moduleDReg
DReg((out,
out,in,
in,clock,
clock,reset
reset););
input
inputin,
in,clock,
clock,reset;
reset;
output
outputout;
out;
register
registerout;
out;
always
always@
@((posedge
posedgeclock
clockor
orposedge
posedge
reset
reset))
begin
begin
ifif((reset
reset==
==1b1
1b1))out
out==0;
0;
else
elseout
out==in;
in;
end
end
endmodule
endmodule

An if statement decode control signals at the beginning of the


behavior

ELEN 468 Lecture 14

11

Registered Combinational
Logic
module
modulereg_and
reg_and((y,
y,a,
a,b,
b,c,
c,
clk
clk););
input
inputa,
a,b,
b,c,
c,clk;
clk;
output
outputy;
y;
reg
regy;
y;
always
always@
@((posedge
posedgeclk
clk))
yy==aa&&bb&&c;
c;
endmodule
endmodule

clk

ELEN 468 Lecture 14

12

Shift Register
module
moduleshift4
shift4((out,
out,in,
in,clock,
clock,reset
reset););
input
inputin,
in,clock,
clock,reset;
reset;
output
outputout;
out;
reg
reg[3:0]
[3:0]data_reg;
data_reg;
assign
assignout
out==data_reg[0];
data_reg[0];
always
always@
@((negedge
negedgereset
resetor
orposedge
posedge
clock
)
clock )
begin
begin
ifif((reset
reset==
==1b0
1b0))data_reg
data_reg==4b0;
4b0;
else
elsedata_reg
data_reg=={{in,
in,data_reg[3:1]
data_reg[3:1]};
};
end
end
endmodule
endmodule

ELEN 468 Lecture 14

Figure 9.10, page


361

13

Counter
module
moduleripple_counter
ripple_counter((count,
count,clock,
clock,toggle,
toggle,reset
reset););
input
inputclock,
clock,toggle,
toggle,reset;
reset; output
output[3:0]
[3:0]count;
count;
reg
reg[3:0]
[3:0]count;
count; wire
wirec0,
c0,c1,
c1,c2;
c2;
assign
c0
=
count[0];
assign
c1
assign c0 = count[0]; assign c1==count[1];
count[1]; assign
assignc2
c2==
count[2];
count[2];
always
always@
@((posedge
posedgereset
resetor
orposedge
posedgeclock
clock))
ifif((reset
reset==
==1b1
1b1))count[0]
count[0]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[0]
count[0]==~count[0];
~count[0];
always
always@
@((posedge
posedgereset
resetor
ornegedge
negedgec0
c0))
ifif((reset
reset==
==1b1
1b1))count[1]
count[1]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[1]
count[1]==~count[1];
~count[1];
always
always@
@((posedge
posedgereset
resetor
ornegedge
negedgec1
c1))
ifif((reset
reset==
==1b1
1b1))count[2]
count[2]==1b0;
1b0;
else
if
(
toggle
==
1b1
)
count[2]
else if ( toggle == 1b1 ) count[2]==~count[2];
~count[2];
always
@
(
posedge
reset
or
negedge
always @ ( posedge reset or negedgec2
c2))
ifif((reset
reset==
==1b1
1b1))count[3]
count[3]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[3]
count[3]==~count[3];
~count[3];
endmodule
endmodule

ELEN 468 Lecture 14

Fig. 9.14
Page
366

14

Synthesis of Explicit Finite


State Machines
A behavior describing the synchronous activity
may contain only one clock-synchronized event
control expression
There is always one and only one explicitly
declared state register
State register must be assigned value as an
aggregate, bit select and part select
assignments to state register is not allowed
Asynchronous control signals must be scalars in
the event control expression of behavior
Value assigned to state register must be
constant or a variable that evaluates to a
constant
ELEN 468 Lecture 14
15

Comparison of Explicit and


Implicit FSMs
Explicit FSM

Implicit FSM

Explicit State
Register

Yes

No

State Encoding

Yes

No

Sequence of
States

Specified

Implicit

Sequence
Control

Explicit
assignment to
state register

Specified by
procedural
flow

ELEN 468 Lecture 14

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State Encoding Example


#

Binary

Gray

Johnson

One-hot

000

000

0000

00000001

001

001

0001

00000010

010

011

0011

00000100

011

010

0111

00001000

100

110

1111

00010000

101

111

1110

00100000

110

101

1100

01000000

111

100

1000

10000000

ELEN 468 Lecture 14

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State Encoding
A state machine having N states will
require at least log2N bits register to store
the encoded representation of states
Binary and Gray encoding use the
minimum number of bits for state register
Gray and Johnson code:

Two adjacent codes differ by only one bit


Reduce simultaneous switching

Reduce crosstalk
Reduce glitch

ELEN 468 Lecture 14

18

One-hot Encoding
Employ one bit register for each state
Less combinational logic to decode
Consume greater area, does not matter for
certain hardware such as FPGA
Easier for design, friendly to incremental
change
case and if statement may give different
result for one-hot encoding
define
definestate_0
state_03b001
3b001
Runs faster
define
definestate_1
state_13b010
3b010
define
definestate_2
state_23b100
3b100

ELEN 468 Lecture 14

19

Rules for Implicit State


Machines
Synchronizing signals have to be aligned to the same clock
edge in an implicit FSM, the following Verilog code will not
synthesize

always
always@
@((posedge
posedgeclock
clock););
begin
begin
aa<=
<=b;
b;
cc<=
<=d;
d;
@(
@(negedge
negedgeclock
clock))
begin
begin
ee<=
<=f;f;
gg<=
<=h;
h;
end
end
end
end

ELEN 468 Lecture 14

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Resets
Strongly recommended that every
sequential circuit has a reset signal
Avoid uncertain initial states
Specification for output under reset
should be complete, otherwise
wasted logic might be generated

ELEN 468 Lecture 14

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Gated Clock
Pro: reduce power consumption
Con: unintentional skew

dat
a
cloc
k
clock_enabl
e

Q
flipflop

ELEN 468 Lecture 14

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Design Partitions
Partition cells such that connections
between partitions is minimum
1

2
3

ELEN 468 Lecture 14

a
2
c
23

Example: Sequence
Detector
Single bit serial input

Synchronized to falling edge of clock

Single bit output

Assert if two or more successive 0 or 1 at input


Active on rising edge of clock

Cloc
k
Input
Outpu
t

ELEN 468 Lecture 14

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State Transition Diagram


State0

0/0
0/1
State1
Input 0

Start
state

1/0
1/1

1/0
0/0
ELEN 468 Lecture 14

State2
Input 1

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