Microprocessor

Chapter 1 Part B

Intel 8086/8088
Microprocessor family

Introduction :Unlike 8085, 8086 and 8088 can be operated in

two modes : Minimum mode and Maximum mode.

In this chapter we study the topics related to
Minimum mode and Maximum mode operation of
8086. Topics include
Clock generator (IC 8284)
Bus Transceiver (IC 8286)
Bus latching (IC 8282)
Bus Controller (IC 8288)
Minimum mode operation and Maximum mode

operation.
Let us begin with signal description of 8086.

Signal Description of 8086

In order to implement many situations in

the microcomputer system the 8086 and

8088 has been designed to work in two
operating modes.
Minimum Mode
Maximum Mode

The minimum mode is used for a small

systems with a single processor and

maximum mode is for medium size to large
systems which often include two or more
processors.

Pin Diagram of 8086

The 8086 signals can be categorized

in three groups.
Signals having common functions in both

minimum and maximum modes.

Signals having special functions for
minimum mode.
Signals having special functions for
maximum mode.

Pin Diagram of 8086

Pin Out of 8086

Pin Diagram of 8086

40 pins of 8086 are

Supply pins (03 pins)

Clock related pins (03 pins)

Address & data pins (21

pins)

Interrupt pins (02 pins)

Other control pins (03

pins)

Mode multiplexed signals

(08 pins)
[ MIN mode & MAX
mode signal ]

I. Supply Pins
Three supply pins are
VCC (Pin no. 40) : Used for power supply
i.e. +5v

Two separate GROUND pins (Pin no. 1 &

20 ) for heat dissipation.

II. Clock related Pins

CLK (pin no.19): provides the basic timing

for the processor.
8086 does not have an on chip clock
generator, hence an external clock
generator (8284) provides this signal.
RESET (pin no. 21): It causes the processor
to immediately terminate its present
activity. The 8284 clock generator provides
this signal.
It clears all the flags registers, the
instruction Queue, the DS,ES,SS and IP

Clock related Pins Cont

READY (Pin no.22): it is an

acknowledgement from the addressed

memory or I/O that it will complete data
transfer.
p samples the READY input between T2 &
T3 of a M/C cycle.
If READY pin is low, p insert wait-state
between T2 & T3, until READY becomes
HIGH.

Address & data pins (21 pins)

AD0-AD15 (pin no. 2 to 16 and 39):
AD0-AD15:These are the time multiplexed address data lines

i.e. for sometimes they have address and for sometimes

data.
It gives the address A0-A15 during T1 of a machine cycle

(where ALE=1).
It gives the data D0-D15 after T1 of a machine cycle.
A16/S3 to A19/S6 (pin no.35 to 38)

These lines works as address bus (A16 to A19) during T1 of

every machine cycle.

T2 onwards these lines works as status signals S3-S6

Address & data pins (21 pins)

Cont.
S3 & S4 gives the status of memory segment

currently accessed.
S5 gives the status of the interrupt Enable Flag
updated every clock cycle.
S6 goes low when 8086 controls the shared
system bus.
S4

S3

Segment Accessed

Extra Segment

Stack Segment

Code Segment

Data Segment

Address & data pins (21 pins)

Cont.
BHE*/S7 (Pin no.34) This line carries the BHE*

(Bus High Enable) signal during T1.

BHE* & A0 are together to access a word/Byte from
the memory as shown in next slide. (Memory bank
Operations)
Status line S7 Used by 8087 numeric coprocessor
to determine whether the CPU is a 8086 or 8088.
* Indicate active LOW pin.

Memory Bank
8086 processors organize memory into two banks:

an "even" bank and an "odd" bank. Figure

illustrates the connection to the CPU (D0-D7
denotes the L.O. byte of the data bus, D8-D15
denotes the H.O. byte of the data bus):

Interrupt pins Pin no. (17 &

18 )
NMI (pin no. 17):
Non Maskable Interrupt: an edge triggered input which
causes a type 2 interrupt i.e. on receiving an interrupt
on NMI the p executes INT2 and transfers the control to
location 2*4=00008H in the interrupt vector table.
It reads 4 locations starting from this address to get
values for IP & CS of the ISR (Interrupt Service Routine).
It is not maskable internally by software.
A transition from a LOW to HIGH initiates the interrupt at
the end of the current instruction.
This input is internally synchronized.

(Cont..)
INTR (pin no.18): INTERRUPT

This is a maskable level triggered interrupt.

To get the vector no. for the interrupt following
Procedure is followed;
on receiving an interrupt on INTR pin the p
executes 2 INTA pulses
1. First INTA* pulse
the interrupting device is
indicated for its interrupt being accepted while the
device calculates the vector no.
2. Second INTA* pulse
the interrupting device send
the vector no. to the p on the data lines.
Control shift to location pointed by IP & CS which are
loaded from IVT (Interrupt Vector Table) at vector no.4

Other control pins (03 pins)

TEST* (Pin no.23): It is an active LOW pin

dedicated for 8087 co-processor.

In minimum mode it is connected to GND.
In maximum mode , whenever the coprocessor is busy it makes this pin HIGH.
TEST* input is examined by WAIT instruction.
If the TEST pin is HIGH p enters idle state; till
TEST* pin becomes LOW i.e. 8087 is free.

Other control pins (cont..)

MN/MX* (pin no. 33):

This is an input signal to 8086 that indicates the

processor has to work in which mode.
If this signal is HIGH 8086 is in Minimum mode i.e.

Single processor system.

If this signal is LOW 8086 is in Maximum mode i.e.
Multiprocessor system.

RD* (pin no.32):

RD* (pin no.32): it is an active LOW output

signal. when it is LOW 8086 reads from

memory or an I/O device.

Mode multiplexed signals

HOLDRQ*/GT* (pin no.31 ):
In minimum mode this line carries the HOLD input
signal from other master requesting a local bus.
The DMA controller issues the HOLD signal to
request for the system bus.
In response 8086 completes the current bus cycle
& releases the system bus.
In maximum mode it carries the bidirectional
RQ*/GT* (Request/Grant) signal.
In external bus master (8089 or 8087) sends an
active LOW pulse to request for the control over
the system bus.
8086 gets back the system bus only after
external bus master sends an active low release
pulse on the same line.

Mode multiplexed signals (contd..)

HLDA-- RQ1*/GT1* (pin no. 30)
In minimum mode this line carries the HLDA signal.
This signal is issued by 8086 after releasing the system

bus.
In maximum mode it functions as RQ1*/GT1* which is same
as RQ0*/GT0*; but is lower priority.
WR*-- LOCK* (pin no. 29):
In minimum mode this line carries the WR* signal indicates

a write operation when this pin is low.

It is used with M/IO* to write to memory or IO device.
In maximum mode it functions as the LOCK* output line.
When 8086 executes an instruction with the LOCK prefix
this signal is active low remains active till next instruction,
indicating the external bus master cannot take control of
the system bus.

Mode multiplexed signals (contd..)

DEN*---S0* (Pin no. 26):

In minimum mode it carries the DEN*
signal & is used to enable the data
transceivers (bidirectional buffer IC
8286).
In maximum mode it carries the signal
So*. So* is a status signal given to 8288.
In maximum mode bus controller (IC
8288) generates the DEN signal for
8286.

Mode multiplexed signals (contd..)

DT/R*---S1 (pin no. 27):

In minimum mode it carries the DT/R*

signal indicating data transmit or receive.

This signal goes low for a read operation
& high for a write operation.
In maximum mode it carries the signal
S1*. S1* is the status signal given to
8288.
In maximum mode bus controller issues
the DT/R* signal to 8286.

Mode multiplexed signals (contd..)

M/IO*---S2* (pin no. 28):
In minimum mode it carries the M/IO* signal to

distinguish between memory & IO access.

In maximum mode it carries S2* signal. S2* is
status signal given to 8288.
In maximum mode S2* S1* & S0* are used to
generate the appropriate control signal.
S2*

S1*

S0*

Characteristics

0 (LOW)
0
0
0
1(HIGH)
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Interrupt acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive

Mode multiplexed signals (contd..)

ALEQS0 (pin no.25):
In minimum mode it carries the ALE
signal, which is used to demultiplexed the
address data lines by latching the address.
In maximum mode it carries the QS0
signal.
It is used with QS1 to indicate instruction
Queue Status.
In maximum mode bus controller 8288
issues the ALE signal (to latches IC 8282).

Mode multiplexed signals (contd..)

INTA QS1 (pin no. 24):
In minimum mode it carries the INTA* signal.
It is issued in response to an interrupt on the INTE
line.
In maximum mode it carries the QS1 signal.
In maximum mode bus controller issues the INTA*
QSsignal
QS0 8086).
Characteristics
(to
1

0(LOW)

0
1
1(HIGH) 0
1
1

No operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent byte from Queue

Clock Generator 8284

As microprocessor needs external clock generator circuit

to generate reset, ready clock signals.

A Clock Generator chip 8284 is used.
It is 18 pin IC.
There are three sections.
It is used for i) Reset Logic ii) Clock Circuit iii) Ready
Logic.
Reset Logic
This

is a active LOW signal when received at the I/P of 8284,will

reset the functions of 8284.
Has RES signal as input and gives Reset as output. The O/P
Reset signal can be used to reset the 8086.

Clock section :
Inputs :
o Crystal connected as input at X1/X2
o external frequency input (EFI)
o (F/C) frequency/clock select input
o Clock synchronization (CSYNC)
Output:
o CLK

8284 (Cont..)
READY (Pin no.5): It is an active HIGH signal

generated by 8284.This pin is connected directly

to the READY input of 8086.
This o/p signal is synchronized with TWO ready
input signal RDY1 & RDY2.
These are the input signal available from the
external device on pin no 4 & 6.
Whenever an external device wants to introduce a
WAIT T-state for proper data transfer, it will
activate the RDY1 or RDY2 input.
A synchronized READY signal will be produced by
8284 and applied to 8086.

8284 Block

8284 (Cont..)
X1 X2 are the pins of crystal oscillator. It

generates the clock frequency signal for 8284.

F/C* (Frequency/Crystal Select) (Pin no. 13):
It is clock source select input pin.
If F/C*=0 Then the processor clock signal is produced

by using the crystal as clock source.

If F/C*=1 then the external source connected at EFI
pin is used for generation of processor clock
External Frequency Input (EFI) (Pin no. 14):
If the user has external high frequency (other than

8284)

Or external variable frequency source, it can

be used to drive
multiple 8284, Then that source is connected
at the input pin of

8284 (Cont..)
Clock synchronization (CSYNC) (Pin no.1):
It synchronizes the CPU clock to an external

event.
When CSYNC=1 the CLK and PCLK (peripheral
CLK) O/P are forced to become 1.
When CSYNC=0 then the next positive clock from
the next selected frequency source (crystal or EFI)
will start the clock generation.
CLK (Clock) (Pin no. 8 ): This is a output pin and
processors clock signal is available on this pin.
CLK pin is connected to the clock input of 8086.

8282 An Octal Latch : A latch is a register with specific purpose.

This group of D flip flop is used to hold values to be

output to other devices.

The address and data bus of 8086 are multiplexed bus
that means same pin (AD0-AD15) is used to carry
address as well as data on time sharing basis.
The remaining A16/S3 to A19/S6 four address lines are also
multiplexed with S3 to S6 and hence are to be
demultiplexed.
The ALE signal is used to enable external latches to
store the address.
Also the BHE*/S7 signal is to be demultiplexed.
If we are using full 20 - bit address then we will
require 3 (8282) chips.

Use of 8282

8286 Bus Transceiver

It is used for driving the 16 bit data bus from the

multiplexed address data bus of 8086.

It is a 20 pin IC.
It is used for buffering of 8 bit data line (Bidirectional Buffer).
It has signal T for direction & OE as enable.
OE is used for enabling the appropriate driver to put
his data onto respective bus.
T (Transmit) an input pin of 8286.
If T=1 A0-A7 acts as an input and B0-B7 output.
If T=0 A0-A7 acts as an output and B0-B7 input.
Two pins DT/R and DEN are used to be connected in
minimum mode to set the direction and to enable
data.
Two 8286 chips will be required.

Fig. 8286 Transceivers

Use of 8286

8288 Bus Controller

8086 has three kind of buses Address, data,

control.
8086 provides three control buses RD*, WR*
M/IO*
A decoder IC 74138 is used to convert these

three lines into four signals

1. MEMR* (Memory Read)
2. MEMW* (Memory Write)
3. IOR* (I/O Read)
4. IOW* (I/O Write)

8288 Bus
Controller

Bus Controller 8288

.

Bus Controller 8288 (Cont..)

S0, S1, S2 inputs: Status bus bits from

processor. Decoded by the 8288 to

produce the normal control signals
CLK input: From the 8284A clock
generator
ALE output: Address latch enable
output for de-multiplexing address/data
DEN output: This signal is used to
enable data transceivers onto either
LOCAL or SYSTEM BUS.
opposite polarity to DEN output in
minimum mode.
DT/*R output: Data transmit/Receive
output to control direction of the bi
directional data bus.
INTA output: Acknowledge a hardware

Bus Controller 8288 (Cont..)

IORC output: This command instruct an I/O
device to drive its data onto the data bus.
IOWC output: This command instruct an
I/O device to read from the data bus.
AIOWC output: (Advanced Input / Output
control signal) This instruction issues an I/O
write command earlier in machine cycle to
give I/O devices an earlier indication of a
write instruction.
MRDC output: (Memory read control
signal) This command line instruct the
memory to drive its data onto data bus.
MWTC output: (Memory write control
signal) This command line instruct the

Bus Controller 8288 (Contd..)

AMWC output: (Advanced Memory write control signal)

This issues a memory write command earlier in the machine

cycle to give memory devices an early indication of write
instruction.

MCE/*PDEN output: (Master cascade/Peripheral data

output)
when IOB=0 MCE occurs during an interrupt sequence and
serves to read a cascade address from a master PIC onto
the data bus.
When IOB=1 PDE enables the data bus transceivers for the
I/O bus during I/O instruction

AEN input: Address Enable input. Used by the 8288 to

enable memory control signals. Supplied by a bus arbiter in

a multiprocessor system
CEN input: (Command Enable)
Enables the generation of command outputs from the 8288.

Modes of Operations of 8086

Two modes of operations of 8086 are
Minimum modes : is also known as SINGLE

processor mode.
Maximum mode: Is also known as MULTIPLE
PROCESSOR mode

Minimum Mode Configuration of 8086

Signals in Minimum Mode

Pin No.24 (INTA*)

It is an active low interrupt acknowledge signal which is out put signal

after reception of interrupt giving away three pulses providing

acknowledgement and type of interrupt.

Pin No.25 (ALE)

It is address latch enable signal used for de-multiplexing of
address/data line and statuss .It is never grounded.!!!
Pin No. 26 (DEN*)
It is active low data enable output signal used to inform trans-receiver
that processor is ready to transmit/receive data depending on status
of DT/R
Pin No.27 (DT/R*)
It is an output data flow control signal for direction representation of
flow of data
Pin No.28 (M/IO*)
It is a control signal to specify memory or IO operation with processor.
Pin No.29 (WR*)
It is an active low control signal for writing data on memory or IO
Pin No. 30 (HLDA)
It is a DMA operation control acknowledgement signal for HOLD
request. It remains high till DMA operation is on. It becomes low when
HOLD is low.
Pin No. 31 (HOLD)
It is a DMA operation control signal for DMA request. It is an input
signal

Overvie
w
In minimum mode configuration address (A0-A19)

is generated using ALE through (Ic8282/74373).

Data (D0-D15) through (Ic8286/74245).
CLK signal, Ready, Reset is provided by clock
generator (8284).
VCC and Two GND are +5V and earth.
Control signals are generated using
RD*,WR*,M/IO* with 74138.
Signal MN/MX* is connected to Vcc.
NMI/INTR are received from external interrupt
controller with INTA* as acknowledgement.
HOLD/HLDA from/to DMA controller.
TEST* is also received externally.
DEN* & DT/R* are used by Trans-receiver

Signals in maximum mode

Pin No.24/25 QS0/QS1
o These are queue status signals used for

specifying the status of queue during

previous clock cycle.
Pin No.26/27/28 S0*,S1*,S2*
o These are status signals to used to specify
the type of operation performed by the
processor in current bus cycle.
Pin No.29 LOCK*
o This is used when LOCK prefix is used with
some instruction and other processor are
prohibited from accessing any of the buses.
Pin No.30/31 RQ*/GT0* & RQ*/GT1*
o These are replacement signals for
HOLD/HLDA for requesting for bus signals

Maximum mode Configuration Ckt.

Overview
In maximum mode configuration address (A0-A19) is

generated using ALE through (Ic8282/74373).

Data (D0-D15) through (Ic8286/74245).
CLK signal, Ready, Reset is provided by clock
generator (8284).
Bus controller (8288) provides ALE signal to 8282
and also the required signals for 8286 DEN & DT/R*.
DEN is active high and needs to be inverted
VCC and Two GND are +5V and earth.
MN/MX* is connected to GND
NMI/INTR are received from external interrupt
controller with INTA* as acknowledgement from
8288.
Memory and IO control signals are also provided by
8288 as MRDC, MWTC, IORC, IOWC
Status signals s0*,s1*,s2* are provided as input to
8288.
RQ*/GT* 0&1 are replacement signals for
HOLD/HLDA

Microprocessor 8088
The main difference between p 8086 and p 8088 are
1.
2.
3.
4.
5.

8088 has 8-bit data bus while 8086 has 16 bit data bus.
BHE*/S7 pin of 8086 can be replaced by SS0* pin in 8088.
The M/IO* pin of 8086 can be replaced by IO/M* pin in
8088.
Both the ps are operated on +5v supply.
Both can drive one 74XX, five 74LSXX, one 74SXX, ten
74ALSXX and ten 74HCXX.