Computer

Organisation:
ICT2101
Lecture(s)2124:
I/O Organisation
By Kavitha Thamadharan

Content
I/O Address Mapping
I/O Programming
I/O Interaction

Polling
Interrupt-Driven
DMA

Introduction to Input/ Output

I/O Interface

Input-output involves the transfer to (or from)

peripheral devices from (or to) the data bus of the
CPU; eg. data transfer to the CRT display, from
the keyboard, to/from a hard-disk drive, to/from a
modem to another computer system.
Input-output operations fall into one of the
following types:

Programmed I/O CPU polls peripherals to check if I/O is

needed
Interrupt I/O-peripheral sends an interrupt request to CPU for
I/O
Direct memory access(DMA) -peripheral writes directly to
memory

Memory & I/O Map

Map The Memory and I/O maps for the

8086/8088 microprocessor.
Isolated

I/O.
Memory mapped I/O.

I/O Ports

Computer systems consist of multiple I/O ports, each

represented by an address.
When the CPU performs an output instruction (I/O write
cycle) the data on the bus must be stored by the port.
Similarly, when an input instruction is executed (I/O read
cycle), the I/O port must gate its data onto the data bus lines.
The 8086 processor has only two I/O instructions: IN and
OUT.
There are two forms of I/O instructions
Direct - The I/O port address is supplied within the instruction and
restricts the access to ports with addresses between 0 and 255.
Indirect - Uses register DX to hold the port address. This allows
access to the full range of I/O ports from 0 to 65,535.

The advantage of the indirect form is that an I/O procedure

can be set up and shared between several peripherals by
passing the port address (in register DX) to the procedure.

IN Instruction

IN instruction will cause a data to be read from

the I/O port to the register AL or AX.
Example :
Direct I/O : IN AL, 20H

Read an 8-bit data from port 20H and store it in register AL

Direct

I/O : IN AX, 50H

Read a 16-bit data from port 50H and store it in register AX

Indirect

I/O : IN AL, DX

Read an 8-bit data from port which address is specified by

register DX and store it in register AL.

OUT Instruction

OUT instruction will cause a data stored in

register AL or AX to be written to the I/O port.
Example :
Direct I/O : OUT 10H, AL

Write an 8-bit data from register AL to port 10H

Indirect

Write a 16-bit data from register AX to port which address

is specified by register DX

Indirect

I/O : OUT DX, AX

I/O : OUT DX, AL

Write an 8-bit data from register AL to port which address is

specified by register DX

Memory-Mapped I/O

Rather than having an explicit I/O instructions, memorymapped I/O technique reserve specific addresses within
the memory-address space for controlling the I/O
devices. In hardware it appears to be a conventional I/O
port. But because it is mapped to a memory address, it is
accessible in software using any of the memory read or
write instructions.
For example, the instruction MOV BH,[1000] becomes
an input instruction (input the data at port 1000 to
register BH).
The advantage of memory-mapped I/O is that large
number of instructions and addressing modes
available for referencing memory compared to the single
input and output commands available with an I/Omapped port.

Polling

CPU needs to know whether an

I/O port is ready before sending
the data. Similarly, the CPU must
also be free when there is an
incoming data from I/O port.
Older CPU design utilizing CPU
polling when handling I/O
operations.
Therefore, CPU spends a lot of
time checking I/O status instead of
executing instructions.
To make the matter worse, I/O
devices are normally very slow
compare to the CPU. So the CPU
spends most of the time waiting
for the I/O devices to be ready for
reading/writing.

Interrupt-Driven I/O

Improvement over the CPU polling method.

Instead of having the CPU to poll the I/O status, we will let the I/O
device to inform the CPU whenever it is ready.
This is done by adding an interrupt input to the CPU. At the end
of each instruction the processor samples this line. If it is active,
control is transferred to a special interrupt service routine (ISR).

Interrupt-Driven I/O

CPU response to an interrupt :

During time 1 the processor is assumed to be executing
its main task.
At time 2 the peripherals READY flag causes an interrupt
to occur.
After finishing the current instruction at time 3, the CS, IP,
and flag registers are pushed onto the stack at time 4.
Control then transfers to the ISR at time 5.
During time 6 the ISR is executed, terminating with the
instruction IRET (interrupt return).
The CS, IP, and flag registers are recovered from the
stack during time 7 and the original task is resumed at
time 8.

Interrupt Types

The 8086 has seven different interrupt types.

External/Hardware Interrupt: NMI and INTR are
external interrupt requested via hardware (NMI and
INTR are actually two interrupt pins of the 8086).
Software Interrupt: INT n, INTO, and the special
single-byte INT 3 breakpoint instruction are software
interrupts placed as desired within a program.
Internal Interrupt: The divide-by-0 and single-step
interrupts are initiated by the CPU : the former if the
quotient produced by a divide instruction exceeds the
capacity of the destination register, and the latter at
the completion of each instruction, if TF is set.

Concept of DMA

When transferring a large number of bytes of data, CPU

is too slow. Why????

Function of Intel DMAC

Quantitative Comparison:

While the 8237 can transfer a byte of data

between I/O peripheral and memory in only 4
clocks, the 8088 would take 39 clocks.

Direct Memory Access (DMA)

Interrupt-driven I/O offers performance improvement

over CPU polling but still, CPU needs to be involved for
every single byte or word read/write.
When a text file is output to a disk drive, that data must
first be read from memory into the CPU and then
transferred to the disk drive. The microprocessor is an
unnecessary middleman in this process, with the
result that the transfer rate is decreased.
By DMA, the peripheral is synchronized to main
memory, not the microprocessor.

Processing DMA

DMA steps:

The actual function of DMA is to act as a primary function

of a P without the process of fetching and decoding an
instruction.

Direct Memory Access (DMA)

During a block input byte transfer, the following

sequence occurs as the data byte is sent from the
interface to the memory:

1.

The interface sends the DMA controller a request for DMA service.
A Bus request is made to the HOLD pin (active High) on the 8086
microprocessor and the controller gains control of the bus.
A Bus grant is returned to the DMA controller from the Hold
Acknowledge (HLDA) pin (active High) on the 8086 microprocessor.
The DMA controller places contents of the address register onto the
address bus.
The controller sends the interface a DMA acknowledgment, which
tells the interface to put data on the data bus. (For an output it
signals the interface to latch the next data placed on the bus.)
The data byte is transferred to the memory location indicated by the
address bus.

2.
3.
4.
5.

6.

Direct Memory Access (DMA)

7.
8.
9.
10.
11.
12.

The interface latches the data.

The Bus request is dropped, the HOLD pin goes Low, and the
controller relinquishes the bus.
The Bus grant from the 8086 microprocessor is dropped and the
HLDA pin goes Low.
The address register is incremented by 1.
The byte count is decremented by 1.
If the byte count is non-zero, return to step 1, otherwise stop.

Types of DMA

Two types of DMA cycles are possible :

Sequential

DMA - the DMAC first performs a read

operation, fetching the data byte into the DMAC.
Next, a write operation is performed, transferring the
data byte to the I/O port. The opposite sequence is
also possible - read a byte from the I/O port, write the
byte to memory.
Simultaneous DMA - With this technique the read
and write operations are performed at the same time.
Data does not flow through the DMAC at all, but
directly from memory to the I/O port (or vice versa).
The result is a factor-of-2 speed improvement over
the sequential approach.

DMA

Several possible DMA transfers:

1. Memory to peripheral
2. Peripheral to memory
3. Memory to memory
4. Peripheral to peripheral

Before the data transfer can occur, the CPU must

program the DMAC for the type of transfer that is to
take place, the destination and source addresses,
and the number of bytes to be transferred.
For a given DMA type, there are three ways (modes)
of mixing the DMA cycles among normal processor
bus cycles.

DMA Modes

In byte or single mode, the DMAC, after gaining control of

the system buses, transfers a single data byte. This is used
when the peripheral device is very slow (i.e. mouse,
external modem, etc).
The burst or demand mode is intended for peripherals that
have high-speed data buffers (i.e. hard disk). After gaining
control of the buses, data is transferred until the peripherals
READY flag is no longer active. The advantage of this
technique is that the buffers can be filled very rapidly by the
DMAC and then emptied at the peripherals leisure.
A third type of DMA is called continuous or block mode
DMA. This is similar to burst mode. This technique is very
effective, with a high-speed peripheral (i.e. USB devices)
that can keep up with the DMAC.

DMA Modes