Introduction and Overview

of Electronic Packaging

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 Introduction and Overview of
Microelectronic Packaging
• An electronic package is defined as that portion of an electronic
structure that serves to protect an electronic/electrical
element from its environment and the environment from the
electronic/electrical element.
•
• In addition to providing encapsulation for environmental
protection, a package must also allow for complete testing of
the packaged device and a high-yield method of assembly to
the next level of integration.
•

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 The Package is essential

• Bridge Between the Components and the External World

• Physical Scale Translator Between the Component Features
and the Surrounding Environment
• Product Differentiator to Keep Pace with Device Requirement in
Increased Performance (Functionality/Complexity) and
Reduced Cost

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 The Package Serves Multiple
Functions

• Protection (Environmental Management of Device)

• Connectivity & Routing (Electrical, Optical, Material)
– Including Power Management & Signal Integrity
• Mechanical Stress Control
• Thermal Management
• Testability And Burn-in

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 Packaging is Multidisciplinary
• Materials Engineering
– Materials Used (Innovation, Development & Production
Support)
– Materials Interactions
– Microstructural Evolution
– Environmental Management Issue
– Deformation & Failure Mechanisms & Modeling
• Electrical Engineering
– Electrical Component
– Power Management/Distribution
– Signal Integrity
– Electrical/Optical/Magnetic Fields & Interactions
– Impact on Material Characteristics
– Numerical Analysis
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 Packaging is Multidisciplinary

• Mechanical Engineering
– Stress Management
– Thermal Management
– Impact on Electrical And Material Characteristics
– Thermo-mechanical Performance & Methodologies
– Numerical Analysis
• Industrial Engineering
– Assembly Process management & Automation
– Reliability Issues & Accelerated Testing
– Assembly Process Effect on Materials, Mechanical
& Electrical Characteristics

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 Functions of an Electronic Package
• Functions that a package must provide:


– A structure to physically support the chip



– A physical housing to protect the chip from the environment



– An adequate means of removing heat generated by the

chips or system


– Electrical connections to allow signal and power access to

and from the chip.


– A wiring structure to provide interconnection between the

chips of an electronic system.

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Functions of Packages

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Hierarchical Electronic Packaging

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 Hierarchical Electronic Packaging

Level 0: Gate-to-gate interconnections on a monolithic silicon



chip
Level 1: Packaging of silicon chips into dual-in-line packages


(DIPs), small outline integrated circuit (SOICs), chip carriers,

multichip packages, and so on, and the chip-level
interconnects that join the chip to the lead frames.
Level 2: Printed wiring board (PWB), also referred to as printed


circuit board (PCB), level of interconnections. Printed

conductor paths connect the device leads of components to
PWBs and to the electrical edge connectors for off-the-board
interconnection.

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 Hierarchical Electronic Packaging

Level 3: Connections between PWBs, including PWB-to-PWB



interconnections or card-to-motherboard interconnections.

Level 4: Connections between two subassemblies. For


example, a rack or frame may hold several shelves of

subassemblies that must be connected together to make
up a complete system.
Level 5: Connections between physically separate systems


such as host computer to terminals, computer to printer,

and so on.
•
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 First Level Interconnection

§ First level packaging ( or interconnection) refers to the

technology required to get electrical signals into and out of
a single transistor or IC; in other words, the connections
required between the bonding pads on the IC and the pins
of the package. This is generally accomplished by wire
bonding, flip-chip bonding, or Tape-Automated Bonding.
•

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 Wire Bonding

• The oldest method, but is still the dominant method used today,
particularly for chips with a moderate number of inputs/outputs(I/O)
(~200).
• This technique involves connecting gold or aluminum wires between
the chip bonding pads, located around the periphery of the chip, and
the contact points on the package.
• This process has been automated for many years, but it is still time
consuming because each wire requires two bonding operations, and
must be attached individually.
• Other limitations of wire bonding include the requirement for minimum
spacing between adjacent bonding sites to provide sufficient room
for the bonding tool, the number of bonding pads that can be located
around the periphery of the chip, signal delay, and crosstalk
between adjacent wires.


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 Flip-Chip Bonding

• The chip is mounted upside down onto a carrier, module, or PWB. Electrical
connection is made via solder bumps. The solder bumps are located
over the surface of the chip in a somewhat random pattern or an array
so that periphery limitation, such as that encountered in wire bonding,
does not limit the I/O capability. The I/O density is primarily limited by the
minimum distance between adjacent bonding pads on the chip and the
amount of chip area that can be dedicated to interconnection.
Additionally, the interconnect distance between chip and package is
minimized since bumps can essentially be located anywhere on the chip.
• Although this technique is attractive for use in multi chip packaging
technology because chips can be located very close together, weakness
of solder joints due to thermal expansion mismatch of the chip-bond-
substrate, heat removal from the back of the chip, and difficulty
inspecting the solder joints after the chip has been attached to the
substrate offer special challenges to the packaging specialist.



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 Second Level Interconnection

Level 2 interconnection refers to the electrical

connection of an IC to a circuit board , the most common
one being a conventional PWB . Following level 1
interconnection , single IC chips normally undergo
encapsulation in either plastic or ceramic based
packages prior to connection to a PWB .
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 Variations of Packages
•

• Package-to-Board attachment
• Pin-Through-Hole (PTH), Surface Mount Technology (SMT)
• Chip-to-Package interconnection
• Wirebond, TAB, Flip Chip
• I/O locations
• Peripheral, Area Array
• Package materials
• Plastic, Ceramic, Thin Film

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 Package-to-Board Attachment
• Insertion (PTH) type
• DIP (Dual In Line Package)
• SIP (Single In Line Package)
• PGA (Pin Grid Array Package)
• Surface Mounting type
• SOP (Small Outline Package)
• QFP (Quad Flat Package)
• BGA (Ball Grid Array Package)
•
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 Peripheral Packages

Dual In Line Package



8–48 pins


Single Outline Package



24 –48 pins


Quad Flat Package



48 –128 pins, up to 384 pins



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Area Array Packages

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 Chip to Package Interconnection
• Flip Chip Package vs Wirebond Package
•
•
•
•
•
•
• The electrical performance of wire-bonds is the
lowest.
•
•
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Multi chip Module (MCM)
•MCM:a single electronic package
containing more than one IC.
•The ICs are interconnected through
a substrate.
•A Motorola 68040 microprocessor and
four dual-port SRAMs in one package

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3D Stacking

• Three-Dimensional Stacking:
• Chips are stacked together.
• The industry desire to reduce product
size, weight, and cost while providing
extra performance (shorter
interconnects that lower capacitance
and inductance, reducing crosstalk,
and lower power consumption) and
increasing functionality, has driven
3D packaging of both chips and
packages.
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