Beruflich Dokumente
Kultur Dokumente
Interfacing
8086/8088
16-bit Microprocessor
Launched in 1978
16-bit Data bus
20-bit Address bus
8086/88 Architecture
BIU
EU
8086/88 Architecture
CPU is divided into
1. Bus Interface Unit(BIU)
2. Execution Unit(EU)
BIU
BIU handles all transfers of data and
addresses on the buses for Execution Unit
EU
Tells the BIU where to fetch instructions
and data from
Decodes instructions
Execute instructions
Add
Subtract
AND
OR
XOR
Increment
Decrement
Flag Register
Flip Flop
Indicates some conditions produced by
execution of an instruction
Controls certain operations of EU
Flag Register
Six conditional flags in this group are
Carry Flag
Parity Flag
Auxiliary carry Flag
Zero Flag
Sign Flag
Over Flow
Three Control Flags
Trap Flag
Interrupt Flag
Direction Flag
Flag Register
X
OF DF IF
TF
SF
ZF
AF X
PF
CF
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
The Queue
if the BIU is not busy...the EU is
decoding or executing without the need
of any buses...it can pre-fetch up to 6
instruction bytes
these instructions are stored in a
FIFO register set called a queue
an example of pipelining
Segment Registers
the 220 bytes of addresses are divided in to 4
64KB segments
code segment - CS register stores upper 16 bits of its
starting address
where executable program is stored
stack segment - SS register stores upper 16 bits of its
starting address
stores addresses and data while a subprogram is
executed
data segment - DS register stores upper 16 bits of its
starting address
holds data
extra segment - ES register stores upper 16 bits of its
starting address
holds more data
Advantages of Memory
Segmentation
Allow the memory capacity to be 1Mb
even though the addresses associated
with the individual instructions are only 16
bits wide.
Facilitate the use of separate memory
areas for the program, its data and the
stack.
Permit a program and/or its data to be put
into different areas of memory each time
the program is executed.
Multitasking becomes easy.
Instruction Pointer(IP)
contains the 16-bit address of the next
code byte in the code segment
this is called an offsetit must be added to
the address contained in the CS register,
which is called the base
example:
CS contains the value 348AH
IP contains the value 4214H
whats the physical address of the next code
byte?
you can represent an address in segment
base:offset form348A:4214
4489FH
38AB4H
CS
IP
3
3
Physical Address
348A0H
Top of Code
Segment
Code Byte
Start of Code
Segment
Addressing Modes
Different ways in which processor can
access data is called addressing modes
Data Addressing Modes
Program memory addressing modes
Stack Memory Addressing modes
Register Addressing
Immediate Addressing
Direct Addressing
Register Indirect Addressing
Base-plus-Index Addressing
Register Relative Addressing
Base relative-plus-index addressing
Register Addressing
Transfers a byte or word from the
source register or memory location to
destination register or memory location
Eg: MOV CX,DX
Immediate Addressing
Transfers the source immediate byte or
word of data into destination register or
memory location
Eg: MOV AL,20H
Direct Addressing
Moves a byte or word between a memory
location and a register
Does not support memory-to-memory
transfer
Eg: MOV AL,[1234H]
Base-plus-Index Addressing
Transfers a byte or word between a
register and a memory location addressed
by a base register(BP or BX) plus an index
register (DI or SI)
Eg: MOV DX, [BX+DI]
Program Memory-Addressing
Modes
Used with JMP and CALL instructions,
consists of three different forms
Direct Program Memory Addressing
Relative Program Memory Addressing
Indirect Program Memory Addressing
Request / Grant pin may appear that both signals are active low.
But in reality, Request signal goes low first (input to processor),
and then the processor grants the request by outputting a low on
the same pin.