Lecture 4

Combinational Logic Implementation

Technologies
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 4

Outline

Review of Combinational Logic Technologies

Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,
5.5 5.6, 5.7, 6.2

ECE C03 Lecture 4

Programmable Arrays of Logic Gates

Until now, we learned about designing Boolean
functions using discrete logic gates
We will now describe a technique to arrange AND
and OR gates (or NAND and NOR gates) into a
general array structure
Specific functions can be programmed
Can use programmable logic arrays (PLA) or
programmable array logic (PAL)

ECE C03 Lecture 4

PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of
AND gates

Product
terms

Dense array of
OR gates

Outputs

ECE C03 Lecture 4

Why PALs/PLAs Work

Equations
Example:

F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A

Personality Matrix
Product Inputs
Outputs
term
A B C F0 F1 F2 F3
0 1 1 0
AB
1 1 BC
- 0 1 0 0 0 1
AC
1 - 0 0 1 0 0
BC
- 0 0 1 0 1 0
1 0 0 1
A
1 - -

Key to Success: Shared Product Terms

Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
Reuse
1 = term connected to output
of
0 = no connection to output
terms

ECE C03 Lecture 4

Example of PALs and PLAs

All possible connections are available
before programming

ECE C03 Lecture 4

Example of PALs and PLAs (Contd)

Unwanted connections are "blown"

Note: some array structures

work by making connections
rather than breaking them

ECE C03 Lecture 4

Alternative Representations
Short-hand notation
so we don't have to
draw all the wires!

Notation for implementing

F0 = A B + A' B'
F1 = C D' + C' D

ECE C03 Lecture 4

Design Example
Multiple functions of A, B, C

ABC
A

F1 = A B C

F2 = A + B + C

C
A

F3 = A B C

F4 = A + B + C

C
ABC

F5 = A xor B xor C

ABC

F6 = A xnor B xnor C

ABC
ABC
ABC
ABC
ABC

ECE C03 Lecture 4

F1

F2

F3

F4 F5

F6

Differences Between PALs and PLAs

PAL concept implemented by Monolithic Memories
constrained topology of the OR Array

A given column of the OR array

has access to only a subset of
the possible product terms

PLA concept generalized topologies in AND and OR planes

ECE C03 Lecture 4

10

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Design Example: BCD-to-Gray Code

Converter
Truth Table
K-maps
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X

X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X

Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X

Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X

AB
00

01

11

10

00

01

11

10

CD

AB
00

01

11

10

00

01

11

10

CD

D
C

K-map for W

K-map for X

AB

AB

00

01

11

10

00

01

CD

Minimized Functions:

00

01

11

10

00

01

CD

D
11

W = A+ B D + B C
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'

D
11

10

C
10

K-map for Y

K-map for Z

ECE C03 Lecture 4

11

Programmed PAL

0
0
0

0
0
AB C D

ECE
Lecture
4 product terms per
eachC03
OR gate

12

Non-Gate Logic
So far we have seen:
AND-OR-Invert
PAL/PLA

Generalized Building Blocks

Beyond Simple Gates

Kinds of "Non-gate logic":

switching circuits built from CMOS transmission gates
multiplexer/selecter functions
decoders
tri-state and open collector gates
read-only memories

ECE C03 Lecture 4

13

Steering Logic: Switches

Voltage Controlled Switches
Channel
Region

Gate
Oxide
Source

Silicon Bulk

Drain

n-type Si
p-type Si

"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is
formed

ECE C03 Lecture 4

14

Switching or Steering Logic

Voltage Controlled Switches

Gate
Source

Drain

Logic 1 on gate,
Source and Drain connected

nMOS Transistor
Gate
Source

Drain

Logic 0 on gate,
Source and Drain connected

pMOS Transistor

ECE C03 Lecture 4

15

Logic Gates with Steering Logic

Logic Gates from Switches
+5V

A
+5V

A
+5V

AB

A+ B

Inverter

NAND Gate

NOR Gate

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors

ECE C03 Lecture 4

16

Inverter with Steering Logic

Inverter Operation
+5V

"1"

+5V

"0"

Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND

"0"

"1"

Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD

ECE C03 Lecture 4

17

NAND Gate with Steering Logic

NAND Gate Operation
"1"

"0"

"1"

+5V

"1"

+5V

"0"

A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND

"1"

A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD

ECE C03 Lecture 4

18

NOR Gate with Steering Logic

NOR Gate Operation
"0"
+5V

"1"

"0"

+5V

"1"

A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD

"0"

"0"

A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND

ECE C03 Lecture 4

19

CMOS Transmission Gate

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control

Control

In

Out

Control

Switches

In

Control

Out

Control

Transistors

ECE C03 Lecture 4

In

Out

Control

Transmission or
"Butterfly" Gate

20

Selection/Demultiplexing

Selector:
Choose I0 if S = 0
Choose I1 if S = 1

0
S

1
S

Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1

Z0
I

S
Z1
S

ECE C03 Lecture 4

21

Use of Multiplexers or Demultiplexers

A

Demultiplexers

Multiplexers

Demultiplexers

Multiplexers

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination
interconnect
ECE C03 Lecture 4
22

Well-formed Switching Logic

Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I

Z1
S
"0"
S

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

ECE C03 Lecture 4

23

Use of Multiplexers/Selectors
Multi-point connections

A0
Sa

A1

B0

B1

MUX

MUX

Multiple input sources

Sb

Sum

Ss

DEMUX

S0

Multiple output destinations

S1

ECE C03 Lecture 4

24

General Concept of Using Multiplexers

2

data inputs, n control inputs, 1 output

n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1

A
0
1

Functional form
Logical form

ECE C03 Lecture

Z
I0
I1

I1
0
0
0
0
1
1
1
1

I0
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

Z
0
0
1
0
0
1
1
1

Two alternative forms

4for a 2:1 Mux Truth Table
25

Use
of
Multiplexers/Selectors
2:1

I0

Z = A' I 0 + A I 1

mux

I1

A
I0
I1
I2
I3

4:1
mux

A
I0
I1
I2
I3

8:1
mux

I4
I5
I6
I7

Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +

A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z =
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux

ECE C03 Lecture 4

26

Alternative Implementation
A

I0

I1

I2

I3

Gate
GateLevel
Level
Implementation
Implementation
of
of4:1
4:1Mux
Mux

Transmission
TransmissionGate
Gate
Implementation
Implementationof
of
4:1
Mux
4:1 Mux

thirty six transistors

twenty transistors

ECE C03 Lecture 4

27

Design of Large Multiplexers

Large multiplexers can be implemented by cascaded smaller ones

I0
I1
I2
I3

0 4:1
1 mux
2
3S S

I4
I5
I6
I7

0 4:1
1 mux
2
3 S1 S0

8:1
mux
0 2:1
mux
1 S

Control signals B and C simultaneously

choose one of I0-I3 and I4-I7
Z

Control signal A chooses which of the

upper or lower MUX's output to gate to Z
I0

I1

1 S
C

I2

I3

1 S

0
1

Alternative 8:1 Mux Implementation

C
I4

I5

1 S
C

I6

I7

1 S

ECE C03 Lecture C4

2
3 S0

S1

28

Multiplexers/Selectors as General
Purpose Blocks
n-1

:1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1

0
1
2
3
4
5
6
7

8:1
MUX
S2 S1 S0
A

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F
1
0
1
0
0
0
1
1

C
C
0

C
C
0
1

0
1
2
3

4:1
MUX
S1
A

S0
B

"Lookup Table"

ECE C03 Lecture 4

29

Generalization of Multiplexer/Selector
Logic F
I I I
1

n-1 Mux
control variables
single Mux
data variable

0
1

0
0

0
1

1
0

1
1

Four possible
configurations
of the truth table rows

In

In

Can be expressed as
a function of In, 0, 1

Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
Multiplexer
Implementation
TTL
TTLpackage
packageefficient
efficient
May
be
gate
inefficient
May C03
be gate
inefficient
ECE
Lecture
4

1
D
0
1
D
D
D
D

0
1
2
3
4
5
6
7

8:1
mux

S2
A

S1
B

S0
C

30

Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2

outputs

control inputs (called select S) represent Binary index of output to which

the input is connected
data input usually called "enable" (G)
1:2 Decoder:
O0 = G S; O1 = G S
2:4 Decoder:
O0 = G S0 S1

3:8 Decoder:
O0 = G S0 S1 S2
O1 = G S0 S1 S2
O2 = G S0 S1 S2

O1 = G S0 S1

O3 = G S0 S1 S2

O2 = G S0 S1

O4 = G S0 S1 S2

O3 = G S0 S1

O5 = G S0 S1 S2
O6 = G S0 S1 S2

ECE C03 Lecture

O7 =4G S0 S1 S2

31

Alternative Implementations
G

Output0

Select

/G
Select

Output0
Output1

Output1

1:2 Decoder, Active Low Enable

1:2 Decoder, Active High Enable

/G

Select0

Output0

Output0

Output1

Output1

Output2

Output2

Output3

Output3

Select0

Select1

2:4 Decoder, Active High Enable

Select1

2:4 Decoder, Active Low Enable

ECE C03 Lecture 4

32

Switch Level Implementations

Select

Select
G

Output

Select
Select

Output
0
Select
Select

"0"
Select

Output
1

Select

Select

Output

Select

Naive, Incorrect Implementation

All outputs not driven at all times

Select
"0"
Select

Correct 1:2 Decoder Implementation

ECE C03 Lecture 4

33

Switch Implementation of 2:4 Decoder

Select

Select

Output

Operation of 2:4 Decoder

"0"
"0"

S0 = 0, S1 = 0
Output

"0"

three diagonal paths

"0"

one straight thru path

Output

"0"
"0"

Output

"0"
"0"

ECE C03 Lecture 4

34

Decoder as a Logic Building Block

Enb

3:8
dec

S2
A

S1
B

S0

0
1
2
3
4
5
6
7

ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC

Decoder Generates Appropriate

Minterm based on Control Signals

Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

ECE C03 Lecture 4

35

Decoder as a Logic Building Block

Enb

4:16
dec

S3 S2 S1 S0
A

B C

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A BCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD

F1

F2

F3

If active low enable, then use NAND gates!

ECE C03 Lecture 4

36

Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V

n
2 -1

Dec

Word Line 0011

Word Line 1010

n-1
Address

Bit Lines

ECE
C03 Lecture
Internal
Organization

37

Implementing Logic with ROMs

F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1

Address

ROM
8 w ords by
4 bits

A B C
address

F0

F1

F2

outputs

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F0
0
1
0
0
1
1
0
0

F1
0
1
1
0
0
0
0
1

F2
1
1
0
0
1
0
0
0

F3
0
0
0
1
1
0
1
0

Word Contents

F3

ECE C03 Lecture 4

38

ROMs vs PLAs
Memory array

Not
Notunlike
unlikeaaPLA
PLA
structure
with
structure withaa
fully
fullydecoded
decoded
AND
ANDarray!
array!

Decoder

2n word
lines

n address
lines

2n words by
m bits

m output
lines

ROM vs. PLA:

ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained
fan-ins
OR planes
ECE
C03onLecture
4

39

Summary

Review of Combinational Logic Technologies

Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,
5.5 5.6, 5.7, 6.2

ECE C03 Lecture 4

40