Transistor Types

Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
Oct 2010

CMOS VLSI Design

MOS Integrated Circuits

1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

CMOS VLSI Design

1980s-present: CMOS
processes for low idle power2

Oct
2010

Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
1,000,000,000

Integration Levels

100,000,000
10,000,000

Transistors

Intel486

1,000,000
80286

100,000

Pentium 4
Pentium III
Pentium II
Pentium Pro
Pentium

SSI:

10 gates

MSI: 1000 gates

Intel386

8086
10,000
1,000

8008
4004

LSI:

8080

10,000 gates

VLSI: > 10k gates

1970

1975

1980

1985

1990

1995

2000

Year

Oct 2010

CMOS VLSI Design

The MOS Transistor

Polysilicon

Aluminum

JFET Junction Field Effect Transistor

MOSFET - Metal Oxide Semiconductor Field Effect Transistor
VLSI Design
n-channel MOSFET (nMOS) CMOS
& p-channel
MOSFET (pMOS)

The MOS Transistor

Gate Oxide
Gate
Source

Polysilicon

n+

Drain
n+

p-substrate

Field-Oxide
(SiO2)

p+ stopper

Bulk Contact

CROSS-SECTION of NMOS Transistor

CMOS VLSI Design

nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
capacitor
Source
Gate
Drain
Polysilicon
Even though gate is
SiO2
no longer made of metal
n+

n+
p

Oct 2010

CMOS VLSI Design

bulk Si

nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source

Gate

Drain
Polysilicon
SiO2

n+
p

Oct 2010

n+
bulk Si

CMOS VLSI Design

nMOS Operation Cont.

When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source

Gate

Drain
Polysilicon
SiO2

n+
p

Oct 2010

n+
bulk Si

CMOS VLSI Design

pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source

Gate

Drain

Polysilicon
SiO2

p+

p+
n

Oct 2010

bulk Si

CMOS VLSI Design

Power Supply Voltage

GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

Oct 2010

CMOS VLSI Design

10

Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
d
nMOS

pMOS

g=1

d
OFF

ON

OFF

ON
s

Oct 2010

g=0

CMOS VLSI Design

11

CMOS Inverter
A

VDD

0
1

A
A

Oct 2010

GND
CMOS VLSI Design

12

CMOS Inverter
A

VDD

0
1

OFF

A=1

Y=0

ON
A

Oct 2010

GND
CMOS VLSI Design

13

CMOS Inverter
A

VDD
ON
A=0

Y=1

OFF
A

Oct 2010

GND
CMOS VLSI Design

14

CMOS NAND Gate

A

Oct 2010

Y
A
B

CMOS VLSI Design

15

CMOS NAND Gate

A

Oct 2010

ON
A=0
B=0

CMOS VLSI Design

ON
Y=1
OFF
OFF

16

CMOS NAND Gate

A

Oct 2010

OFF
A=0
B=1

CMOS VLSI Design

ON
Y=1
OFF
ON

17

CMOS NAND Gate

A

Oct 2010

ON
A=1
B=0

CMOS VLSI Design

OFF
Y=1
ON
OFF

18

CMOS NAND Gate

A

Oct 2010

OFF
A=1
B=1

CMOS VLSI Design

OFF
Y=0
ON
ON

19

CMOS NOR Gate

A

Oct 2010

A
B
Y

CMOS VLSI Design

20

3-input NAND Gate

Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

A
B
C
Oct 2010

CMOS VLSI Design

21

Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND

VDD

SiO2
n+ diffusion

n+

n+

p substrate
nMOS transistor

Oct 2010

p+

p+
n well

p+ diffusion
polysilicon
metal1

pMOS transistor

CMOS VLSI Design

22

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
A
GND

VDD

p+

n+

n+

p+

n+

n well

p substrate
substrate tap

Oct 2010

p+

well tap

CMOS VLSI Design

23

Inverter Mask Set

Transistors and wires are defined by masks
Cross-section taken along dashed line

GND

VDD
nMOS transistor

pMOS transistor
well tap

substrate tap

Oct 2010

CMOS VLSI Design

24

Oct 2010

CMOS VLSI Design

25

Detailed Mask Views

Six masks
n well

n-well
Polysilicon

Polysilicon

n+ diffusion

n+ Diffusion

p+ diffusion

p+ Diffusion

Contact

Contact
Metal
Oct 2010

Metal

CMOS VLSI Design

26

Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2

p substrate

Oct 2010

CMOS VLSI Design

27

Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Oct 2010

CMOS VLSI Design

28

Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light

Photoresist
SiO2

p substrate

Oct 2010

CMOS VLSI Design

29

Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist

Photoresist
SiO2

p substrate

Oct 2010

CMOS VLSI Design

30

Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

Oct 2010

CMOS VLSI Design

31

Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranha etch
Necessary so resist doesnt melt in next step

SiO2

p substrate

Oct 2010

CMOS VLSI Design

32

n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well

Oct 2010

CMOS VLSI Design

33

Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

n well
p substrate

Oct 2010

CMOS VLSI Design

34

Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide

p substrate

Oct 2010

n well

CMOS VLSI Design

35

Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

p substrate

Oct 2010

n well

CMOS VLSI Design

36

N-diffusion
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact

p substrate

Oct 2010

n well

CMOS VLSI Design

37

N-diffusion (cont.)
Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate

Oct 2010

CMOS VLSI Design

38

N-diffusion (cont.)
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

n+

n+
p substrate

Oct 2010

n+
n well

CMOS VLSI Design

39

N-diffusion (cont.)
Strip off oxide to complete patterning step

n+

n+
p substrate

Oct 2010

n+
n well

CMOS VLSI Design

40

P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+
p substrate

Oct 2010

p+

p+

n+

n well

CMOS VLSI Design

41

Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+

n+

n+

p+

p+

n+

n well
p substrate

Oct 2010

CMOS VLSI Design

42

Metalization
Sputter on copper / aluminum over whole wafer
Pattern to remove excess metal, leaving wires

Metal

Oct 2010

CMOS VLSI Design

43

Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size scales ~X0.7 every 2 years both lateral
and vertical
Moores law
Normalize feature size when describing design rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
Todays = 0.01 m (10 nanometer = 10-8 meter)
Oct 2010

CMOS VLSI Design

44

Simplified Design Rules

Conservative rules to get you started

Oct 2010

CMOS VLSI Design

45

Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2sometimes called 1 unit
In f = 0.01 m process, this is 0.04 m wide, 0.02
m long

Oct 2010

CMOS VLSI Design

46