8086 PIN-OUTS and PIN functions, Clock Generator (8284A), Bus Buffering and Latching,

and BUS Timing

PIN-OUTs

MIN MODE

MAX MODE

PIN Function:
AD7-AD0: address/data bus. Whenever ALE = 1, these lines contains the right most 8 bits
of memory address or I/O port number or ALE = 0, these lines contains data. These
pins are at their high-impedance state during a hold acknowledge.
AD15-AD8: These lines contains the upper-half memory address or I/O port number. These
pins are at their high-impedance state during a hold acknowledge.
A19/S6-A16/S3: address/status bus. These pins are at their high-impedance state during a hold
acknowledge. S6 is always a logic zero, S5 indicates the condition of the IF flag bit.

RD:

Read Signal. If = 0, data bus is receptive to data from memory and I/O devices
connected to the system. This pin floats to a high-impedance state during a hold
acknowledge.
READY: input is controlled to insert wait states into the timings of a microprocessor.
If = 0, microprocessor remains idle. If = 1, no effect on the operation of P.

INTR:

Interrupt Request is used to request a hardware interrupt. If INTR = 1 and IF = 1,

P enters an interrupt acknowledge cycle. This pin and INTA are connected to the
8259 interrupt controller chip.
TEST:
(Only used in MAX mode) input pin is tested by the wait instruction. If pin = 0, the
WAIT instruction functions as NOP, If pin = 1, wait for a pin to become low. It most
often connected to 8087 numeric coprocessor.
NMI:
Non-Maskable Interrupt input is similar to INTR except that it doesn't check the
IF flag bit. If NMI is activated, this interrupt input uses interrupt vector 2.
RESET: input causes the P to reset itself if this pin is held high for a minimum of 4 clock
cycles. When ever P is reset, it begins instruction at memory location FFFF0H and
disables future interrupts by clearing the IF flag bit.
CLK:
CLOCK pin provides the basic timing signal to the microprocessor. It must have a
duty cycle of 33% (HIGH for 1/3 of the clocking period and Low for 2/3 of the
clocking period) to provide proper internal timing for the 8086/8088.
VCC:
Power Supply input connection to a +5.0 V, 10% signal to the P.
GND:
Ground connection is the return for the power supply. 8086/8088 has two pins, both
must be connected to ground for proper operation.
MN/MX: Minimum/Maximum pin selects the mode operation for P. If minimum mode is
selected, this pin must be connected directly to +5.0 V.

BHE/S7 : BUS High Enable pin is used to enable the most-significant data bus bits (D15-D8)
during a read or a write operation. The state of S7 is always a logic 1.
M/IO :
pin selects memory or IO. This pin indicates that the P address bus contains either
a memory address or an IO port address. This pin is at high-impedance state during
a hold acknowledge.
WR :
WRITE line/pin is a strobe that indicates that 8086/8088 is outputting data to a
memory or IO devices.
INTA :
Interrupt Acknowledge signal is a response to the INTR input pin. This pin is
used to gate the interrupt vector number onto the data bus in response to an interrupt
request.
ALE :
Address Latch Enable shows that 8086/8088 address/data bus contains address
information. This address can be a memory address or IO port number. ALE pin
doesn't float during a hold acknowledge.
DT/R :
Data Transmit/Receive signal shows that P data bus is transmitting or receiving
data. This signal is used to enable external data bus buffers.
DEN :
Data Bus Enable activates data bus buffers.
HOLD : Hold Input Requests a direct memory access (DMA). IF = 1, P stops executing
software and places its address, data and control bus at the high impedance state.

HLDA :

HOLD Acknowledge indicates that has entered the hold state.

CLOCK GENERATOR (8284A)

Its an ancillary component to the Ps. Specially designed for use with the
8086/8088 P. It provides the following basic functions or signal:
Clock generation
RESET synchronization
READY synchronization
TTL-level peripheral clock signal
PIN Functions:
GND :
Ground pin connects to ground.
VCC :
Power Supply input connection to a +5.0 V with a tolerance of 10%.
RES:
RESET IN is an active low input to the 8284A. It is connected to RC network that
provides power-on reset.
X1and X2 : Crystal IN are the pins to which crystal is attached. Crystal frequency must be
3 times the desired frequency for the P. 24MHz is a maximum crystal attachable.
F/C:
Frequency/Crystal pin provides an option for clock generation. If = 0, the clock is
generated by the 8284A with the help of Crystal Oscillator. If = 1, it expects to
receive clocks at EFI pin.

EFI :
External Frequency In. External frequency is connected to this pin.
CSYNC : Clock Synchronization in systems with multiple processor, to allow several 8284A
chips to be connected together and synchronized.
RDY1 and AEN1:
They are used together to provide a ready signal to P, which will insert
WAIT state to the CPU read/write cycle.
RDY2 and AEN2: (Bus Ready and Address Enable) Designed to allow for a multiprocessing
system.
ASYNC : Ready Synchronization select. Used with devices that are not able to adhere to the
very strict RDY setup time requirement. Making the timing design of the system
easier with slower logic gates.
RESET : It provides input signal to 8086/8088 RESET pin. It is activated by the RES pin.
OSC :
Oscillator provides a clock frequency equal to the crystal oscillator.
CLK :
Clock is an output clock frequency equal to 1/3 of crystal oscillator or EFI input
frequency, with a duty cycle of 33%. Connected to the CLK input pin of 8086/8088
and all other devices that must be synchronized with the CPU.
PCLK : Peripheral Clock is 1/6 of the crystal clock with a duty cycle of 50%. Connected to
8253 timer to generate a speaker tones and for other functions.
READY : Connected to the READY pin of P. Used to signal 8086/8088 that CPU needs to
insert WAIT state due to slowness of the devices that the P is trying to contact.

Bus Buffering and Latching:

Before 8086/8088 Ps can be used with memory and IO interfaces, their multiplexed buses must
be demultiplexed. Also buses must be buffered for very large systems. B/C maximum fan-out is 10.

BUS TIMING:
It is essential to understand system bus timing before choosing a memory or IO device for
interfacing to the 8086/8088 P.
Basic Bus Operation:
If data are written to memory
P outputs the memory address on the address bus
Output the data to be written into memory on the data bus
Issues a write (WR) to memory and M/IO

If data are read from memory

P outputs the memory address on the address bus
Issues a read (RD) to memory and M/IO
accepts the data via the data bus

Timing:
Ps uses the memory and IO in clock periods called bus cycles
Each bus cycle = 4 system-clocking periods (T states)

Ex: if clock is operated at 5MHz, 1 bus cycle is complete in 800ns

P can reads or writes data between itself and memory or IO at a maximum
rate of 1.25 million times a second.
8086/8088 has internal queue, and can execute 2.5 million instructions per second (MIPS)

T1 Clocking Period:
Address of memory or IO location is sent out via address bus and address/data bus connections
Control signals ALE, DT/R and M/IO are output
T2 Clocking Period:
RD or WR, DEN and in the case of write, the data to be written appear on data bus
READY is sampled at the end of T2
T3 Clocking Period:
If READY is low at that time T3 becomes a wait state (Tw)
If bus cycle is a read bus cycle, the data bus is sampled at the end of T3
T4 Clocking Period:
All bus signals are deactivated in preparation of next bus cycle