CHAPTER 1

DESIGN COMPILER
INTRODUCTION

DC Ultra
DC Ultra advanced features that are provided in
addition to the DC Expert basic features:
Infrastructure to support multicore execution for faster runtimes
Advanced arithmetic optimization
Integrated datapath partitioning and synthesis capabilities
Advanced timing analysis
Advanced delay optimization algorithms
Automatic leakage power optimization
Register retiming, the process by which the tool moves registers through
combinational
gates to improve timing
The following additional DC Ultra features are available when you run the tool in
topographical mode:
Support for multivoltage and multiple supply designs
Concurrent multicorner-multimode optimization, which reduces iterations and provides
faster time-to-results
Placement and optimization technologies that are shared with IC Compiler place and
route to drive accurate timing and area prediction within synthesis, ensuring a better
starting point for physical implementation

Design Compiler Graphical

The following list is an overview of the Design Compiler Graphical
features that are provided
in addition to the DC Expert and DC Ultra features:
Optimization for multicorner-multimode designs
Reduction of routing congestion during synthesis
Improved area and timing correlation with IC Compiler
Improved runtime and routability in IC Compiler
Ability to create and modify floorplans using floorplan
exploration
Physical guidance technology, which includes enhanced
placement and the capability to
pass seed placement to IC Compiler to improve quality of results
(QoR), correlation, and
routability

DC Explorer
DC Explorer enables you to perform early RTL exploration,
leading to a better starting point for RTL synthesis and
accelerating design implementation
DC Explorer provides the following features:
Efficiently performs what-if analysis of various design configurations
early in the design cycle, even with incomplete design data, to
speed the development of high quality RTL description and
constraints and drive a faster, more convergent design flow
Generates an early netlist, which can be used to begin physical
exploration in IC Compiler
Creates and modifies floorplans very early in the design cycle with
access to IC Compiler design planning
Performs preliminary synthesis quickly compared to full synthesis,
yet gives you timing and area results typically within ten percent of
the final results produced by Design Compiler in topographical mode

HDL Compiler
The HDL Compiler tool translates Verilog
or VHDL descriptions into a generic
technology (GTECH) netlist, which is
used by Design Compiler to create an
optimized netlist. After the design
meets functionality, timing, power, and
other design goals, you can read the
gate-level netlist into IC Compiler and
begin physical implementation.

Library Compiler
Library Compiler reads the
description of an ASIC library from a
text file and compiles the
description into either an internal
database (.db file format) or into
VHDL libraries. The
compiled database supports
synthesis tools.

Power Compiler
The Power Compiler tool offers a complete
methodology for power, including analyzing and
optimizing designs for static and dynamic power
consumption. It performs RTL and
gate-level power optimization and gate-level power
analysis. By applying the power
reduction techniques available in the Power Compiler
tool, including clock-gating, operand
isolation, multivoltage leakage power optimization,
and gate-level power optimization, you
can achieve power savings, and area and timing
optimization in synthesis.

DFT Compiler and

DFTMAX
The DFT Compiler tool is the Synopsys advanced test synthesis
solution. It enables transparent implementation of design-for-test
capabilities into the Synopsys synthesis flow without interfering with
functional, timing, signal integrity, or power requirements.
The DFT Compiler tool is the Synopsys advanced test synthesis
solution. It enables transparent implementation of design-for-test
capabilities into the Synopsys synthesis flow without interfering with
functional, timing, signal integrity, or power requirements.
The extra patterns needed to achieve high test quality for these
designs can increase both the test time and the test data, resulting in
higher test costs.
DFTMAX compression reduces these costs by delivering 10-100x test
data and test time reduction with very low silicon area overhead.
DFTMAX enables compressed scan synthesis in Design Compiler and
compressed scan pattern generation in TetraMAX ATPG.

Design Vision
The Design Vision tool is the graphical user interface
(GUI) for the Synopsys logic synthesis environment and
provides analysis tools for viewing and analyzing
designs at the generic technology (GTECH) and gate
level.
The Design Vision main window provides menus and
dialog boxes for running frequently used Design
Compiler commands.
It also provides graphical displays, such as histograms
and schematics for visual analysis.
A layout view displays floor plan constraints, critical
timing paths, and congested areas in a single, flat view
of the physical design.

Design Compiler in the Design

Flow

High-Level Design Flow

Tasks

Design Compiler in the Design

Flow

e synthesis design flow consists of the design exploration stage and the final des
plementation stage.

Exploration stage
In the design exploration
stage, you use DC Explorer
to perform
what-if analysis of various
design configurations early
in the design cycle to
speed the development of
high-quality RTL and
constraints and drive a
faster, more convergent
design
flow.

Implementation stage

In the design
implementation stage,
you use the full power
of Design Compiler to
synthesize the design.

Using a Compile Strategy

Design Compiler supports the following compile
flows:
Full compile
Incremental compile
During an incremental compile, Design Compiler can
improve quality of results (QoR) by improving the structure
of your design after the initial compile
In topographical mode, you can perform a second-pass,
incremental compile to enable topographical-based
optimization for post-topographical-based synthesis flows
such as retiming, design-for-test (DFT), DFTMAX, and minor
netlist edits. The primary focus in Design Compiler
topographical mode is to maintain QoR correlation;
therefore, only limited changes to the netlist can be made.

Using a Compile Strategy

cont
Different pieces of your design require
different compilation strategies, such as a topdown hierarchical compile or bottom-up
compile. You need to develop a compilation
strategy before you compile.
Top-down compile
Bottom-up compile
Mixed compile
Use the top-down compile strategy for small hierarchies
of blocks.
Use the bottom-up compile strategy to tie small
hierarchies together into larger blocks.

Optimization Basics
Optimization is the Design Compiler synthesis step that maps the design to an
optimal combination of specific target logic library cells, based on the designs
functional, speed,and power requirements.
Design Compiler calculates two cost functions: one for design rule constraints
and one for optimization constraints.
Optimization accepts a change if it decreases the cost of one component
without increasing more-important costs.
By default, the design rule constraints (transition, fanout, capacitance, and
cell degradation) have a higher priority than the optimization constraints
(delay and area).
Design Compiler performs the following levels of optimization in the following
order:
1. Architectural Optimization
2. Logic-Level Optimization
3. Gate-Level Optimization
Experimenting with speed and area to get the smallest or fastest design is
called exploring the design space.

CHAPTER 2
Working With Design Compiler

Design Compiler Modes

You can use Design Compiler in the following modes.
Wire load mode and topographical mode are tool modes.
When you start Design Compiler, you must choose either wire
load mode or topographical mode.

Multimode and UPF mode are not tool modes.

Multimode allows you to operate the tool under multiple
operating conditions and multiple modes, such as test mode
and standby mode.
UPF mode allows you to specify advanced low-power
methodologies.
Multimode and UPF mode are available only in topographical mode.

 Multimode-Designs are often required to operate

under multiple modes, such as test or standby
mode,and under multiple operating conditions,
sometimes referred to as corners. Such designs
are known as multicorner-multimode designs .
You can use IEEE 1801also known as Unified Power
Format (UPF)commands in a UPF file to specify lowpower design intent for multivoltage designs when you
use the Power Compiler tool.

For details about defining modes and corners and setting up multicorner-multimode analysis, see Optimizing Multicorner-Multimode
Designs.

Invoke tool
When you invoke Design Compiler in wire load or
topographical mode, it automatically executes commands in
three setup files. These files have the same file name,
.synopsys_dc.setup, but reside in different directories. The
files can contain commands that initialize parameters and
variables, declare design libraries, and so on.
1. The Synopsys root directory ($SYNOPSYS/admin/setup)=>
system-wide setup file
2. Your home directory =>This user-defined setup file can contain
variables that define your preferences for the Design Compiler
working environment. The variables in this file override the
corresponding variables in the system-wide setup file.
3. The current working directory=> This design-specific setup file
can contain project-specific or design-specific variables that affect
the optimizations of all designs in this directory.

Starting the Tool in Wire Load

Mode

Design Compiler Startup

Tasks

Redirecting the Output of

Commands

Log Files

Saving Designs and Exiting Design

Compiler

SYNTHESIS FLOW

Multicore Technology
The multicore technology in Design Compiler
allows you to use multiple cores to improve the
tool runtime. During synthesis, multicore
functionality divides large optimization tasks into
smaller tasks for processing on multiple cores.
Enabling Multicore Functionality
prompt> set_host_options -max_cores 6

Measuring Runtime
When you measure the runtime speedup using
multicore optimization, use the wall clock time of
the process.

report_qor

Parallel execution

THANK YOU

BREAK

CHAPTER 3
PREPARING FOR
SYNTHESIS

Preparing your design and constraints for

synthesis

To learn about preparing your design

and constraints for synthesis, see the
following topics:
Managing the Design Data
Partitioning for Synthesis
HDL Coding for Synthesis
Performing Design Exploration
Creating Constraints

Managing the Design Data