MPMC

Term:2015-2016
III Year B.Tech I Sem

Unit-III PPT Slides

I/O Interface

UNIT 3 SYLLABUS
3.0 8086 interfacing
3.1 I/O interface with 8255-PPI
3.1.1 Various modes of operations and interfacing

to 8086,
3.2 Interfacing Keyboard,
3.3 LED Displays,
3.4 stepper motor interfacing and
3.5 A/D converter interface
3.5.1 D/A converter interface
3.6 Interfacing with advanced devices
3.6.1 Memory interfacing to 8086,
3.7 Interrupt structure of 8086,

Contd.

3.7.1 Vector interrupt table,

3.7.2 Interrupt service routine

3.8 Introduction to DOS,BIOS Interrupt

3.9 8259 PIC architecture,
3.9.1 Interfacing Interrupt Controller 8259,
3.10 8257 DMA Controller to 8086
3.11 Introduction to Serial Communication
3.12 Serial data transfer schemes
3.13 Serial Communication standards
3.13.1 RS 232C
3.13.2 IEEE488
3.14 8251 USART architecture and interfacing
3.15Prototyping and trouble shooting.

UNIVERSITYQUESTIONS
1.Show8255PPIinmode1operationandinterfaceto8086.
2.Explaintheinterruptstructureof8086.
3)ExplaintheneedforRS232Cinterface.Explainserialcommunication
standardswithrespecttovoltagelevels.
4.Interface8086tokeyboardanddisplayunit.
5.Explaininterruptserviceroutineconcept.
6.Explain8251USART..
7.ExplainA/DandD/Aconversionmechanism.
8.Explain8259interruptcontrolleralongwithcontrolregisters.
9.ExplaintheinterfacingofRS232to8086.
10.ExplainI/OmappedI/OandmemorymappedI/O.
11.a)Drawandexplaininterruptacknowledgementcycleof8086.
b)Explainthemodewordformatandthecommandwordformatof8251A

3.0

8086 Interfacing

I/O instructions are IN, INS, OUT, and OUTS

Also isolated (direct I/O or mapped I/O) and

memory-mapped I/O, the basic input and

output interfaces, and handshaking.
One type of instruction transfers information
to an I/O device (OUT).
Another reads from an I/O device (IN).
Instructions are also provided to transfer
strings of data between memory and I/O.
INS and OUTS, found except the 8086/8088
6

Input port:

Output port:

3.1 I/O Interface with 8255 -PPI

It is a programmable device.
It is an I/O port chip used for interfacing I/O

devices with microprocessor

Very commonly used peripheral chip
Knowledge of 8255 essential for students in

the Microprocessors
experiments

lab

for

Interfacing

8255 Ports
8255 PPI has three 8-bit ports.
Port A (PA)
Port B (PB)
Port C (PC)

Port C composed of two independent 4-bit

ports: PC7-4 (PC Upper) and PC3-0 (PC
Lower)
Port A, Port B, Port C and Control port
will have the addresses as 7CH, 7DH,
7EH, and 7FH respectively.
9

10

Data Bus buffer:

It is a 8-bit bidirectional Data bus.
Used to interface between 8255 data bus with

system bus.
The internal data bus and Outer pins D0-D7 pins
are connected in internally.
The direction of data buffer is decided by
Read/Control Logic.

Read/Write Control Logic:

This is getting the input signals from control bus

and Address bus

Control signal are RD and WR.
Address signals are A0,A1,and CS.
8255 operation is enabled or disabled by CS.

Group A and Group B control:

Group A and B get the Control Signal from CPU

and send the command to the individual control

blocks.
Group A send the control signal to port A and
Port C (Upper) PC7-PC4.
Group B send the control signal to port B and
Port C (Lower) PC3-PC0.

PORT A:

This is a 8-bit buffered I/O latch.

It can be programmed by mode 0 , mode 1,
mode 2 .

PORT B:
This is a 8-bit buffer I/O latch.
It can be programmed by mode 0 and

mode 1.

PORT C:
This is a 8-bit Unlatched buffer Input and

an Output latch.
It is spitted into two parts.
It can be programmed by bit set/reset
operation.

8255 Operations
The lines A1-A0 with RD, WR and CS form the

following operations for 8255.

8086 Interfacing ICs

14

operation and interfacing to

8086

8255 has three operation modes: mode 0,

mode 1, and mode 2

Mode 0 - Simple Input or Output mode
Mode 1 - Input or Output with Handshake
mode
Mode 2 - Bidirectional Data Transfer mode
15

Mode 0 - Simple Input or

In
this mode, ports A, B are used as two simple 8Output
bit I/O ports & port C as two independent 4-bit
ports.

Each port can be programmed to function as simply

an input port or an output port.

The input/output features in Mode 0 are as

follows.
1. Outputs are latched.
2. Inputs are not latched.
3. Ports dont have handshake or interrupt capability.
16

Handshaking
Many I/O devices accept or release

information slower than the microprocessor.

A method of I/O control called
handshaking or polling, synchronizes the
I/O device with the microprocessor.
An example is a parallel printer that prints a
few hundred characters per second (CPS).

17

Mode 1 - Input or
Output with Handshake
In this mode, handshake signals are exchanged between

the MPU and

peripherals prior to data transfer.

The features of the mode include the following:
1.

Two ports (A and B) function as 8-bit I/O ports.

They can be configured as either as input or output ports.

2.

Each port uses three lines from port C as handshake signals.

The remaining two lines of Port C can be used for simple I/O
operations.

3.

Input and Output data are latched.

4.

Interrupt logic is supported.

18

Example:
The computer send the data to the printer

large speed compared to the printer.

When computer send the data according to
the printer speed at the time only, printer can
accept.
If printer is not ready to accept the data then
after sending the data bus , computer uses
another handshaking signal to tell printer that
valid data is available on the data bus.
Each port uses three lines from port C as
handshake signals

20

 ~STB : The strobe input loads data into the port latch on a
0-to-1 transition.
IBF : Input buffer full is an output indicating that the input
latch contain information.
INTR : Interrupt request is an output that requests an
interrupts.
INTE : The interrupt enable signal is neither an input nor
an output; it is an internal bit programmed via the PC4
(port A) or PC2 (port B) bits.
PC7,PC6 : The port C pins 7 and 6 are general purpose
I/O pings that are available for any purpose.
21

 ~OBF : Output buffer full is an output that goes low when

data is latched in either port A or port B. Goes low on ~ACK.
~ACK : The acknowledge signal causes the ~OBF pin
return to 0. This is a response from an external device.
INTR : Interrupt request is an output that requests an
interrupt.
INTE : The interrupt enable signal is neither an input nor an
output; it is an internal bit programmed via the PC6(Port A)
or PC2(port B) bits.
PC5,PC4 : The port C pins 5 and 4 are general-purpose I/O
pins that are available for any purpose.
22

23

Mode 2 - Bidirectional Data

This mode is used primarily in applications such as
Transfer
data transfer between two computers.

In this mode, Port A can be configured as the

bidirectional port, Port B either in Mode 0 or Mode

1.
Port A uses five signals from Port C as

handshake signals for data transfer.

The remaining three signals from Port C can be

used either as simple I/O or as handshake for port

B.
24

8255: Mode 2 Bi-directional

Operation
Timing diagram
is a combination
of the Mode 1
Strobed Input
and Mode 1
Strobed Output
Timing
diagrams.

25

8255 Control Words

There are 2 control words in 8255.
1.

2.

Mode Definition (MD) Control word

and
Bit Set / Reset (BSR) Control Word

MD control word configures the ports of 8255 as

input or output in Mode 0, 1, or 2.

PCBSR control word is used to set to 1 or reset

to 0 any one selected bit of Port C

1.Mode Definition (MD) Control word

2. Bit Set / Reset (BSR) Control Word

8086 Interfacing ICs

27

 In most keyboards, the key switches are connected

in a matrix of Rows and Columns.
Getting meaningful data from a keyboard requires
three major tasks:
1. Detect a key press
2. Debounce the key press.
3. Encode the key press (produce a standard code
for the pressed key).
Logic 0 is read by the microprocessor when the
key is pressed.
28

Key Debounce:
Whenever a mechanical push-bottom is pressed or
released once, the mechanical components of the
key do not change the position smoothly; rather it
generates a transient response. These may be
interpreted as the multiple pressures and responded
accordingly.

29

30

31

 the 82C55 is decoded at I/O ports 50H53H for

an 8086
port A is programmed as an input port to read the
rows
port B is programmed as an output port to select
a column
a flowchart of the software required to read a key
from the keyboard matrix and debounce the key
is illustrated in Fig.

32

Flow Chart

33

 keys must be debounced, normally with a time delay of

1020 ms
the software uses a procedure called SCAN to scan the
keys and another called DELAY10 to waste 10 ms of time
for debouncing
the main keyboard procedure is called KEY and appears
in Example.
the KEY procedure is generic, and can handle any
configuration from a 1 1 matrix to an 8 8 matrix.
34

35

a
f

b
c

Digit-abcdefg-hex
0-1111110-7E

1-0110000-30

2-1101101-6D

3-1111001-79

4-0110011-33

5-1011011-5B

6-1011111-5F

7-1110000-70

8-1111111-7F

9-1111011-7B

A-1110111-77

B-0011111-1F

C-1001110-4E

D-0111101-3D

E-1001111-4F

F-1000111-47

Fig.1 Internal schematic of a four

winding stepper motor

Fig.2 Winding arrangement of a stepper

motor.

Contd

37

8086 Interfacing ICs

38

Algorithm for ADC interfacing contains the following steps:

Ensure the stability of analog input, applied to the ADC.
Issue start of conversion pulse to ADC
Read end of conversion signal to mark the end of conversion
processes.
Read digital data output of the ADC as equivalent digital output.
Analog input voltage must be constant at the input of the ADC
right from the start of conversion till the end of the conversion to
get correct results. This may be ensured by a sample and hold
circuit which samples the analog signal and holds it constant for
specific time duration. The microprocessor may issue a hold
signal to the sample and hold circuit.
If the applied input changes before the complete conversion
process is over, the digital equivalent of the analog input
calculated by the ADC may not be correct.
39

Fig.3 Timing Diagram Of ADC 0808.

Fig.2 Pin Diagram of ADC 0808/0809

Contd

40

Fig: Interfacing ADC0808 with 8086

Contd

41

Pin Diagram of DAC 0800

Contd

42

Fig:Interfacing DAC0800 with 8086

43

3.6 Interfacing with

Advanced Devices

2 Types

1.Memory mapped I/O

2.I/O mapped I/O (Isolated

I/O)

44

Interfacing
Isolated
I/O: uses the dedicated
Configurations

I/O instructions
(IN, OUT and INS, OUTS) and has its own address
space for I/O ports (0000H-FFFFH), isolated from
the memory address space.

Memory mapped I/O: uses memory reference

instructions (e.g. MOV). So address space is shared

between memory and I/O (used by only one of
them).

Both techniques can be used with Intel processors.

But most Intel-based systems use isolated I/O.

45

a. Isolated I/O
Using dedicated I/O
instructions e.g. IN,
OUT 64 K I/O

Memory:
MOV

bytes
b. Memory-mapped I/O
Using ordinary memory
transfer instructions e.g.
MOV

I/O: IN

MOV
Range of memory addresses
assigned for I/O transfers
Memory

 Memory is a device to store data.

To interfacing with memories, there must be:
address bus, data bus and control signals (chip
enable, output enable etc)
To study memory interface, we must learn how to
connect memory chips to the microprocessor and
how to write/read data from the memory

Content

Address
FFFF

Data

0000

Control signals
Include enable (chip select)
, read/write

Memory Banking

49

INTERFACING
WITH
The figure 1
shows a general
MEMORIES
block diagram of
an 8086 memory
array. In this,
the 16-bit word
memory is
partitioned into
high and low 8bit banks on the
upper halves of
the data bus
selected by BHE,
and AO.

50

a) ROM and EPROM

ROMS and EPROMs are the simplest memory

chips to interface to the 8086.
Since ROMs and EPROMs are read-only devices, A0
and BHE are not required to be part of the chip
enable/select decoding. The 8086 address lines must
be connected to the ROM/EPROM chip chips starting
with A1 and higher to all the address lines of the
ROM/EPROM chips. The 8086 unused address lines can
be used as chip enable/select decoding. To interface
the ROMs/RAMs directly to the 8086-multiplexed bus,
they must have output enable signals. The figure 2
shows the 8086 interfaced to two 2716s. Byte
accesses are obtained by reading the full 16-bit word
onto the bus with the 8086 discarding the unwanted
byte and accepting the desired byte.
51

3.7 Interrupt
Structure
of 8086
Definition:
The meaning of interrupts
is to break the
sequence of operation. While the CPU is executing a
program, on interrupt breaks the normal sequence of
execution of instructions, diverts its execution to some
other program called Interrupt Service Routine
(ISR).After executing ISR , the control is transferred back
again to the main program. Interrupt processing is an
alternative to polling.
Need for Interrupt: Interrupts are particularly useful

when interfacing I/O devices that provide or require

data at relatively low data transfer rate.
52

Classification 8086 INTERRUPTS

256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS
1.

TYPE 0 TO TYPE 4 INTERRUPTSTHESE ARE USED FOR FIXED OPERATIONS AND

HENCE ARE CALLED DEDICATED INTERRUPTS

2.

TYPE 5 TO TYPE 31 INTERRUPTS

NOT USED BY 8086,RESERVED FOR HIGHER PROCESSORS LIKE
80286 ,80386 ETC

3.

TYPE 32 TO 255 INTERRUPTS

AVAILABLE FOR USER,CALLED USER DEFINED INTERRUPTS
THESE CAN BE H/W INTERRUPTS AND ACTIVATED THROUGH INTR
LINE OR CAN BE S/W INTERRUPTS

TYPE 0 DIVIDE ERROR INTERRUPT

QUOTIENT IS LARGE CANT BE FIT IN AL/AX OR DIVIDE BY ZERO

TYPE 1 SINGLE STEP INTERRUPT

USED FOR EXECUTING THE PROGRAM IN SINGLE STEP MODE BY
SETTING TRAP FLAG
TO SET TRAP FLAG PUSHF
MOV BP,SP
OR [BP+0],0100H;SET BIT8
POPF

TYPE 2 NON MASKABLE INTERRUPT

THIS INTERRUPT IS USED FOR EXECUTING ISR OF NMI PIN
(POSITIVE EGDE SIGNAL). NMI CANT BE MASKED BY S/W

TYPE 3 BREAK POINT INTERRUPT

USED FOR PROVIDING BREAK POINTS IN THE PROGRAM

TYPE 4 OVER FLOW INTERRUPT

USED TO HANDLE ANY OVERFLOW ERROR AFTER SIGNED ARITHMETIC

PRIORITY OF INTERRUPTS
INTERRUPT TYPE

PRIORITY

INT0,INT3-INT 255,INTO

HIGHEST

NMI(INT2)

INTR

SINGLE STEP

LOWEST

3.7.1 Interrupt Vector Table IVT

(in
memory)

x86 has 256 interrupts, specified by Type Number or Vector

1 byte of data must accompany each interrupt; specifies

Type
Vector is a pointer (address) into Interrupt Vector Table,
IVT
IVT is stored in memory from 0000:0000 to 0000:03ffh

IVT contains 256 far pointer values (addresses)

Far pointer is CS:IP values

Each far pointer is address of Interrupt Service Routine, ISR

Also referred to as Interrupt Handler

IVT Format
0000:0000
0000:0001
0000:0002
0000:0003
0000:0004
0000:0005
0000:0006
0000:0007

Offset
IP LSB

Interrupt 0

IP MSB

Segment

CS LSB

Offset

CS MSB

Interrupt 1

Segment
Given a Vector, where is the
ISR address stored in memory ?

Offset Type 4
0000:03fc
0000:03fd
0000:03fe
0000:03ff

Offset

Example:
Interrupt 255

Segment

int 36h

Offset = (544) = 216

= 00d8h

Structure of Interrupt Vector Table 8086/88

58

3.7.2 Interrupt Service

Similar to a (ISR)
subroutine
Routine

Attends to the request of an interrupting

source
Clears the interrupt flag
Should save register contents that may be

affected by the code in the ISR

Must be terminated with the instruction RETFIE

When an interrupt occurs, the MPU:

Completes the instruction being executed
Disables global interrupt enable
Places the return address on the stack
59

Interrupt Service Routine

High-priority
interrupts
(ISR)
contd..

The contents of W, STATUS, and BSR registers are

automatically saved into respective shadow registers.

Low-priority interrupts
These registers must be saved as a part of the ISR

If they are affected

RETFIE [s] ;Return from interrupt

RETFIE FAST
;FAST equivalent to s = 1
If s =1: MPU also retrieves the contents of W, BSR,

and
STATUS registers

3.8 DOS & BIOS Introduction

Reserved
INTs

BIOS
functions
(Basic
Input/
Output
System)

INT10 Video services

INT13 Disk Services
INT16 Keyboard functions
INT17 Parallel printer functions

DOS
functions INT21
(Disk
Operating
System)

keyboard
display
printer
disk
date/time
memory management
program control

DOS Functions-Using the Keyboard

DOS INT 21, function 01H: Wait for Keyboard Input

Specification: waits for the user to press a key on the keyboard and
returns the ASCII code.
Input: AH = 01 (function code)

Ex:
MOV ah, 01H; Request keyboard input
INT 21h

Output: AL = ASCII code of the pressed key. The character is echoed to

the video display
Constrain: doesnt return the control to the main program until a key is
pressed.
If the key correspond to an extended ASCII code, AL returns 00. The next
INT 21, function 01 returns in AL the extended ASCII code.

DOS INT 21, function 08H: Console Input without Echo

Specification: similar to function 01 but no echo on video display.
62

Controlling
the
Video
Display
DOS INT 21, function 02H: Display Output
Specification: writes a single character to the display screen, at the current
Ex: MOV AH, 02h;request character display
MOV DL, S
INTcharacter
21h
Input: AH = 02 (function code), DL = ASCII
to be sent to display.

cursor position.

Control characters perform their specific action (0DH = Carriage Return,

0AH = Line Feed, 08H = Backspace, etc.).

DOS INT 21, function 09H: Display A CHARACTER String

Specification: Send to display a string in the current data segment. The
string ends with $ character (not displayed).
Input: AH = 09 (function code), DX = The offset of the first character in the
string.

Ex:
String DB Enter your name: $
MOV AH, 09h; request display
LEA DX, String; load address
INT 21h

63

BIOS Functions: Using the Keyboard

BIOS INT 16, function 00H: Read keyboard Input
Specification: similar to INT21 function 01 but if the pressed key
correspond to an extended ASCII code, AL returns 00 and AH returns the
extended ASCII code. No echo to display.

BIOS INT 16, function 01H: Read keyboard status

Specification: doesnt wait. If the keyboard buffer is empty, ZF is set to 1. If
not, returns the first ASCII code from buffer in the same way like function 00,
and clear ZF.

64

Using the Keyboard(Contd)

BIOS INT 16, function 02H: Return Shift Flag Status
Specification: waits for the user to press a key on the keyboard and
returns the ASCII code.
Input: AH = 02 (function code)
Output: AL = Status of the special function keys:
B7=Insert, B6=Caps Lock, B5=Num Lock, B4=Scroll Lock (active bit=1
=> function active)
B3=Alt, B2=Ctrl, B1=Left Shift, B0=Right Shift (active bit=1 => button
pressed )

65

Controlling the Video Display(Contd)

BIOS INT 10, function 00H: Set Video Mode
Specification: set video mode of the display (ex: mode 1 = 25
linesX40 characters,
mode 3 = 25 linesX80 characters).
Input: AH = 00 (function code), AL = The desired video mode .
BIOS INT 10, function 0FH: Read Current Video Mode
Specification: returns video mode of the display.
Input: AH = 0F (function code)
Output: AL = The current video mode.

66

Controlling the Video Display(Contd)

BIOS INT 10, function 02H: Set Cursor Position
Specification: moves the cursor to specified position (in text mode).
Input: AH = 02 (function code), DH = the row (0-24), DL column (0-79), BH
= page (0)
BIOS INT 10, function 03H: Read the Current Cursor Position
Input: AH = 02 (function code), BH = page (0)
Output: DH = the row (0-24), DL column (0-79)

67

Controlling the Video Display(Contd)

BIOS INT 10, function 0AH: Write Character to Screen
Specification: write multiple times a character to screen at current cursor
position.
Input: AH = 0A (function code), AL = ASCII code, BH = page number, CX =
repeat value.

BIOS INT 10, function 09H: Write Character/Attribute to

Screen
Specification: write multiple times a character to screen at current cursor
position. Specify the video attribute of the character: B7 = blink, (B6 = red, B5
= green, B4 = blue)=background, B3 = intensity, (B2 = red, B1 = green, B0 =
blue)=foreground
Input: AH = 09 (function code), AL = ASCII code, BH = page number,
BL = characters attribute, CX = repeat value.

68

Controlling the Video Display(Contd)

BIOS INT 10, function 08H: Read Character/Attribute from

Screen
Input: AH = 08 (function code), BH = display page (0)
Output: AL = The Character code at the current cursor position, AH = the
attribute byte.

BIOS INT 10, function 06H: Scroll Current Page Up

Input: AH = 06 (function code)
AL = Number of rows to scroll up (0 for entire region)
BH = attribute for scrolled region
CH = Row number at top of region
CL = Column number at left of the region
DH = Row number at bottom of region
DL = Column number at right of the region

Examples: in the textbook!

69

Architecture
FEATURES:
8259 is Programmable Interrupt
Controller (PIC)
It is a tool for managing the interrupt
requests.
8259 is a very flexible peripheral controller chip:
PIC can deal with up to 64 interrupt inputs
interrupts can be masked individually.
various priority schemes can also programmed.
70

71

72

73

Working of 8259
1. One or more of the INTERRUPT REQUEST

lines (IR0IR7) are raised high, setting the

corresponding IRR bit(s).
2. The 8259A evaluates these requests, and

sends an INT to the CPU, if appropriate.

3. The CPU acknowledges the INT and responds

with an INTA* pulse.

4. Upon receiving an INTA* from the CPU group,

the highest priority ISR bit is set and the

corresponding IRR bit is reset.
74

Working of 8259
5. Then 8086 will send one more INTA pulse to

8259.

5.

On this second interrupt acknowledge cycle, 8259

will send an interrupt vector byte of data to the
CPU, which is a pointer of the interrupt to be
processed.

This completes the interrupt cycle.

6. The ISR bit is reset at the end of the 3rd

INTA pulse.

75

76

8259 Command
There are 2 Command Words in 8259.
Words
1.Initialization

Command Words (ICWs):

Before normal operation can begin, each
82C59A in the system must be brought to a
starting point using these command words.

There are 4 ICWs in 8259.

2.Operation Command Words (OCWs): These

are the command words which command the

82C59A to operate in various interrupt modes.

There are 3 OCWs in 8259

77

78

79

ICW3
Format
This word is read only when there is more than one 8259 in the
system and cascading is used, in which case SNGL = 0 in ICW1.

80

81

Operation Command Words

(OCWs)
After the Initialization Command Words (ICWs)
are programmed into the 8259A, the chip is ready
to accept interrupt requests at its input lines.
However, during the 8259A operation, a selection
of algorithms can command the 8259A to operate
in various modes through the Operation
Command Words (OCWs).

OCW1 Format

82

R, SL, EOI: These three bits control the Rotate

and End of Interrupt modes and combinations of
the two.
L2, L1, L0: These bits determine the interrupt
83

84

85

8259 Working Modes

There are 4 different modes for 8259.
1.
2.
3.
4.

Fully nested mode.

Rotating priority mode.
Special mask mode.
Polled mode.

86

87

Fully nested mode

This mode is entered after initialization unless another

mode is programmed.
The interrupt requests are ordered in priority from 0

through 7 (0 highest).
When an interrupt is acknowledged the highest priority

request is determined and its vector placed on the bus.

Additionally, a bit of the Interrupt Service register (ISO-7)

is set.
This bit remains set until the microprocessor issues an

End of Interrupt (EOI) command immediately before

returning from the service routine
If AEOI (Automatic End of Interrupt) bit is set, until the

trailing edge of the last INTA.

88

Rotating priority
mode
In some applications there are a number of interrupting devices
of equal priority.
In this mode, a device after being serviced, receives the lowest

priority.
So a device requesting an interrupt will have to wait, in the worst

case until each of 7 other devices are serviced at most once .

89

Special mask
Some applications
may require an interrupt service routine
mode

to dynamically alter the system priority structure during its

execution under software control.

For example, the routine may wish to inhibit lower priority

requests for a portion of its execution but enable some of

them for another portion.
That is where the Special Mask Mode comes in.
In the special Mask Mode, when a mask bit is set in OCW1,

it inhibits further interrupts at that level and enables

interrupts from all other levels (lower as well as higher)
that are not masked.
Thus, any interrupts may be selectively enabled by loading

the mask register.

90

Polled mode
In Polled mode the INT output functions as it

normally does.
The microprocessor should ignore this output.
This can be accomplished either by not connecting

the INT output or by masking interrupts within the

microprocessor, thereby disabling its interrupt input.
Service to devices is achieved by software using a

Poll command.
The Poll command is issued by setting P = 1 in

OCW3.
91

92

3.10 8257 DMA

Direct memory access (DMA) is a process in which
Controller
to the
8086
an external
device takes over
control of system
bus from the CPU.
DMA is for high-speed data transfer from/to mass

storage peripherals, e.g. hard disk drive, magnetic

tape, CD-ROM, and sometimes video controllers.
The basic idea of DMA is to transfer blocks of data

directly between memory and peripherals.

The data dont go through the microprocessor but

the data bus is occupied.

93

Basic process of DMA Minimum

Mode
The HOLD and HLDA pins are used to receive

and acknowledge the hold request respectively.

Normally the CPU has full control of the system

bus.

In a DMA operation, the peripheral takes over bus

control temporarily.

94

Basic process of DMA Maximum

Mode

The RQ/GT1 and RQ/GT0 pins are used to issue

DMA request and receive acknowledge signals.

Sequence of events of a typical DMA process:

1.

Peripheral asserts one of the request pins, e.g. RQ/GT1

or RQ/GT0 (RQ/GT0 has higher priority)

2.

8086 completes its current bus cycle and enters into a

HOLD state.

3.

8086 grants the right of bus control by asserting a grant

signal via the same pin as the request signal.

4.

DMA operation starts.

5.

Upon completion of the DMA operation, the peripheral

asserts the request/grant pin again to relinquish bus
control.
95

DMA controller
A DMA controller interfaces with several peripherals that

may request DMA.

The controller decides the priority of simultaneous DMA

requests communicates with the peripheral and the CPU,

and provides memory addresses for data transfer.
DMA

controller commonly used

8257/8237 programmable device.

with

8086

is

the

The 8257/8237 is a 4-channel device.

Each channel is dedicated to a specific peripheral device

and capable of addressing 64 K bytes section of memory.

96

8237 - DMA
Controller

97

3.11 Serial Communication Introduction

Parallel Transfer

Serial transfer
Sender

Receiver

S
E
N
D
E
R

R
E
C
E
I
V
E
R

Parallel in serial out register in transmitter

Serial in Parallel out in Receiver
Transmit over single data line
data must be converted from 0, 1 form to

audio tones to transfer it via telephone lines

((MODEM)) ((modulator / demodulator))
No modem is needed for short distances
((keyboard to motherboard))

Serial Comm. Using two

Asynchronous: transfer single character at a time
methods
Synchronous: transfer a block of data
((characters)) at a time
UART: Universal Asynchronous Receiver
Transmitter
USART: Universal Synchronous Asynchronous
Receiver Transmitter

3.12 Serial Data Transfer

Schemes
Simplex

Transmitter

Receiver

Transmitter

Receiver

Receiver

Transmitter

Transmitter

Receiver

Receiver

Transmitter

Half Duplex

Full Duplex

Asynch. Comm. And Data Framing

Frame

Stop Stop
Spac
e

Bit

Bit

0
Mark

d7
Goes out
last

Protocol
Start bit
Stop bit (s)
Chip can be programmed in 5, 6, 7, or 8 bit
characters

Start
1
bit

d0
Goes out
first

2 stop bits is used in older systems due to

slowness of the system to give it sufficient

time to organize itself before transmitting next
byte.
If we use 2 stop bits with ASCII char.
The total number of bits to be transferred is:

2 stop + 1 start +8 ASCII = 11 bits

Which adds 30% overhead time

EXAMPLE
What is the total number of bits to be

transferred when transferring 5 pages each

page with 80x25 ASCII characters and one
stop bit:
For each bit a total of 10 bits is to be transferred
8 ASCII + 1 stop + 1start = 10
80x25x10 = 20,000 bit per page
20,000 x 5 = 100,000 total number of bits

To maintain integrity parity bit may be used

Data transfer Rate:

BPS : bit per second
Baud rate: modem terminology : Number of signal
change per second
We will use them as the same

Example
Calculate the time it takes to transfer the entire data in
prev. example using:
2400 bps
100,000 / 2400 = 41.67 sec

9600 bps
100,000 / 9600 = 10.4 sec

RS 232

RS 232

148
8

148
9
2

C
P
U

UART Chip
TTL output

148
3
9

Ground

Line
Linedriver
driver
Converting
Convertingvoltage
voltage
from
TTL
level
from TTL levelTo
To
RS232
level
RS232 level

Line
Linereceiver
receiver
Converting
Convertingvoltage
voltage
from
RS232
level
from RS232 levelTo
To
TTL
level
TTL level

148
8
Ground

Modem

RS-232 Frame Format

Example

Start bit
ASCII

Idle

Parity

1111010000011
11
A

Stop bit

RS232 standard

RS232

Undefined

+25
v
+3 v

-3 v
1
1 is represented by: -3 to -25
0 is represented by: +3 to +25
-25 v
-3 to +3 is undefined
Line driver Converting voltage from TTL level To RS232

level

Line receiver Converting voltage from RS232 level To TTL

level

high speed data transfer unreliable because

of the capacitance
Increase as length increases

3.13.2 IEEE-488
The IEEE 488 (GPIB) Bus

An example of a bus system is the IEEE 488 general-purpose

interface bus (GPIB) that has evolved from a standard originally
developed in 1965 by Hewlett-Packard. The standard is widely
used to allow instruments to send data over a parallel data bus.
There are three types of devices defined by the standard.
Listeners are devices that receive
data such as monitors or printers.
Instrument
A
Controller
Talker/Listener
(Computer)

Talkers are devices that send

data such as DMMs or signal
Data lines
generators.
Controllers are devices
that determine who can Management
lines
talk and who should
Handshake
listen.
lines

Instrument
B

Instrument
C

Instrument
D

Talker/Listener
(DMM)

Listener
(Printer)

Talker
(Counter)

DI/O1
DI/O2
DI/O3
DI/O4
DI/O5
DI/O6
DI/O7
DI/O8

Data bus

IFC
ATN
SRQ
REN
EOI

Interface management bus

DAV
NRFD
NDAC

Data transfer control bus

Port
Interrupt

Aphysicalinterfaceonacomputerthroughwhichdataarepassedto
orfromaperipheral.
Acomputersignalorinstructionthatcausesthecurrentprocessto
betemporarilystoppedwhileaserviceroutineisrun.

Assemblylanguage
Tristate

AprogramminglanguagethatusesEnglishlikewordsandhasa
onetoonecorrespondencetomachinelanguage.

Atypeofoutputonlogiccircuitsthatexhibitsthreestates:HIGH,
LOW,andhighZ;usedtointerfacetheoutputsofasourcedeviceto
abus.

The UART is a universal asynchronous receiver/transmitter,

which is modeled on the real-world Intel 8251 peripheral
interface adapter component. In the model we are
considering, the UART consists of three main blocks.
a serial transmit block
a serial receive block and
a CPU Interface (I/F) block.

TITLE SERIAL DATA COMMUNICATION BETWEEN TWO PCS

.MODEL SMALL
.STACK
.DATA
MESSAGE DB 'Serial communication via COM2, 4800 ,No P, 1 Stop,8-BIT
DATA.',0AH,0DH
DB ' ANY KEY PRESS IS SENT TO OTHER PC.',OAH,ODH
DB ' PRESS ESC TO EXIT','$'
.CODE
MAIN
PROC
MOV AX, @DATA
MOV DS,AX
MOV AH,09
MOV DX,OFFSET MESSAGE
INT 21H
;initializing COM 2
MOV AH,0
;initialize COM port
MOV DX,01
;COM2
MOV AL,0C3H
;4800 ,N0 P,1 STOP,8-BIT DATA
INT14H

; checking key press and sending key to COM2 to be transferred

AGAIN:MOV AH,01
INT 16H
JZ NEXT
MOV AH,0
INT 16H

;check for key press using INT 16H ,AH=01

;if ZF= 1, there is no key press
;If no key go check COM port

;yes, there is a key press, get it

;notice we must use INT 16H twice,2nd time with

AH=0 to get the char itself. AL=ASCII char pressed

CMP AL, 1BH

JE EXIT
MOV AH, 1
MOV DX,01
INT 14H

;is it esc key?

;yes EXIT
;no. send the char to COM 2 port

;check COM2 port to see there is char. if so get it and display it

NEXT:
MOV AH,03
;get COM 2 status
MOVDX,01
INT 14H
AND AH,01
;AH has COM port status, mask all bits except DO
CMP AH,01
;check DO to see if there is a char
JNE AGAIN
;no data, go to monitor keyboard
MOV AH,02
;yes, COM2 has data: get it
MOVDX,01
INT 14H
;get it
MOV DL,AL
;and display it using INT 21H
MOV AH,02
;DL has char to be displayed
INT21H
JMP AGAIN
;keep monitoring keyboard
EXIT:
MOV AH,4CH
;exit to DOS
INT 21H
MAIN ENDP
END

INTERFACING THE NS8250/16450 UART IN THE IBM PC

The National Semiconductor 8250 and its

variations are the most widely used UART in the

PC.
Due to the fact that the 8250 had a minor bug, the

8250A replaced it.

Later, National Semiconductor made an improved

version of the 8250A and called it 16450.

All the programs written for the 8250/8250A will

run on the 16450.

There is also a CMOS version of the 16450

available called 16C450.

3.15 Prototyping and Trouble

Shooting
Prototyping and construction
Conceptual design
Physical design
Tool support

Two guidelines for design

1. Provide a good conceptual model
allows user to predict the effects of our actions
problem:

designers conceptual model communicated to user through system

image:

appearance, written instructions, system behaviour through interaction,

transfer, idioms and stereotypes

User's model
if system image does notDesign
make model clear and
Model
consistent, user will develop wrong conceptual model
User

Designer
System
System
image

Two guidelines for design

(continued)
2. Make things visible
relations between users intentions, required

actions, and results are

sensible
non arbitrary
meaningful

visible affordances, mappings, and constraints

use visible cultural idioms
reminds person of what can be done and how to do

it

and
construction
What is a prototype?
Why prototype?
Different kinds of prototyping
low fidelity
high fidelity
Compromises in prototyping
vertical
horizontal
Construction

What is a prototype?
In other design fields a prototype is a
small-scale model:
a miniature car
a miniature building or town

What is a prototype?
In interaction design it can be (among other things):
a series of screen sketches
a storyboard, i.e. a cartoon-like series of scenes
a Powerpoint slide show
a video simulating the use of a system
a lump of wood (e.g. iphone)
a cardboard mock-up
a piece of software with limited functionality
written in the target language or in another
language

Why prototype?
Evaluation and feedback are central to interaction
design
Stakeholders can see, hold, interact with a
prototype more easily than a document or a drawing
Team members can communicate effectively
You can test out ideas for yourself
It encourages reflection: very important aspect of
design
Prototypes answer questions, and support
designers in choosing between alternatives

What to prototype?
Technical issues
Work flow, task design
Screen layouts and information
display
Difficult, controversial, critical areas

Low-fidelity Prototyping
Uses a medium which is unlike the final
medium, e.g. paper, cardboard
Is quick, cheap and easily changed
Examples:
sketches of screens, task sequences,
etc
Post-it notes
storyboards
Wizard-of-Oz