ARM instruction set

ARM
ARM
ARM
ARM
ARM
ARM

versions.
assembly language.
programming model.
memory organization.
data operations.
flow of control.

2008 Wayne Wolf

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ARM versions
ARM architecture has been extended
over several versions.
We will concentrate on ARM7.

2008 Wayne Wolf

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ARM assembly language

Fairly standard assembly language:

label

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LDRr0,[r8];acomment
ADDr4,r0,r1

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ARM programming model

r0
r1
r2
r3
r4
r5
r6
r7

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r8
r9
r10
r11
r12
r13
r14
r15 (PC)

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31

CPSR
NZCV

Endianness
Relationship between bit and byte/word
ordering defines endianness:
bit 31

bit 0

byte 3 byte 2 byte 1 byte 0

bit 0

byte 0 byte 1 byte 2 byte 3

little-endian

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bit 31

big-endian

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ARM data types

Word is 32 bits long.
Word can be divided into four 8-bit
bytes.
ARM addresses cam be 32 bits long.
Address refers to byte.
Address 4 starts at byte 4.

Can be configured at power-up as either

little- or bit-endian mode.
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ARM status bits

Every arithmetic, logical, or shifting
operation sets CPSR bits:
N (negative), Z (zero), C (carry), V
(overflow).

Examples:
-1 + 1 = 0: NZCV = 0110.
231-1+1 = -231: NZCV = 0101.

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ARM data instructions

Basic format:
ADDr0,r1,r2
Computes r1+r2, stores in r0.

Immediate operand:
ADDr0,r1,#2
Computes r1+2, stores in r0.

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ARM data instructions

ADD, ADC : add (w.
carry)
SUB, SBC : subtract
(w. carry)
RSB, RSC : reverse
subtract (w. carry)
MUL, MLA :
multiply (and
accumulate)
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AND, ORR, EOR

BIC : bit clear
LSL, LSR : logical
shift left/right
ASL, ASR : arithmetic
shift left/right
ROR : rotate right
RRX : rotate right
extended with C

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Data operation varieties

Logical shift:
fills with zeroes.

Arithmetic shift:
fills with ones.

RRX performs 33-bit rotate, including

C bit from CPSR above sign bit.

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ARM comparison
instructions

CMP : compare
CMN : negated compare
TST : bit-wise test
TEQ : bit-wise negated test
These instructions set only the NZCV
bits of CPSR.

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ARM move instructions

MOV, MVN : move (negated)
MOVr0,r1;setsr0tor1

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ARM load/store
instructions
LDR, LDRH, LDRB : load (half-word,
byte)
STR, STRH, STRB : store (half-word,
byte)
Addressing modes:
register indirect : LDRr0,[r1]
with second register : LDRr0,[r1,r2]
with constant : LDRr0,[r1,#4]
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ARM ADR pseudo-op

Cannot refer to an address directly in
an instruction.
Generate value by performing
arithmetic on PC.
ADR pseudo-op generates instruction
required to calculate address:
ADRr1,FOO
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Example: C assignments
C:
x=(a+b)c;

Assembler:
ADRr4,a
LDRr0,[r4]
ADRr4,b
LDRr1,[r4]
ADDr3,r0,r1
ADRr4,c
LDRr2[r4]
v

;getaddressfora
;getvalueofa
;getaddressforb,reusingr4
;getvalueofb
;computea+b
;getaddressforc
;getvalueofc
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C assignment, contd.
SUBr3,r3,r2
ADRr4,x
STRr3[r4]

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;completecomputationofx
;getaddressforx
;storevalueofx

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Example: C assignment
C:
y=a*(b+c);

Assembler:
ADRr4,b;getaddressforb
LDRr0,[r4];getvalueofb
ADRr4,c;getaddressforc
LDRr1,[r4];getvalueofc
ADDr2,r0,r1;computepartialresult
ADRr4,a;getaddressfora
LDRr0,[r4];getvalueofa
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C assignment, contd.
MULr2,r2,r0;computefinalvaluefory
ADRr4,y;getaddressfory
STRr2,[r4];storey

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Example: C assignment
C:
z=(a<<2)|(b&15);

Assembler:
ADRr4,a;getaddressfora
LDRr0,[r4];getvalueofa
MOVr0,r0,LSL2;performshift
ADRr4,b;getaddressforb
LDRr1,[r4];getvalueofb
ANDr1,r1,#15;performAND
ORRr1,r0,r1;performOR
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C assignment, contd.
ADRr4,z;getaddressforz
STRr1,[r4];storevalueforz

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Additional addressing
modes
Base-plus-offset addressing:
LDRr0,[r1,#16]
Loads from location r1+16

Auto-indexing increments base register:

LDRr0,[r1,#16]!

Post-indexing fetches, then does offset:

LDRr0,[r1],#16
Loads r0 from r1, then adds 16 to r1.
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ARM flow of control

All operations can be performed
conditionally, testing CPSR:
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS,
GE, LT, GT, LE

Branch operation:
B#100
Can be performed conditionally.

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Example: if statement
C:
if(a>b){x=5;y=c+d;}elsex=cd;

Assembler:
;computeandtestcondition
ADRr4,a;getaddressfora
LDRr0,[r4];getvalueofa
ADRr4,b;getaddressforb
LDRr1,[r4];getvalueforb
CMPr0,r1;comparea<b
BGEfblock;ifa>=b,branchtofalseblock
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If statement, contd.
;trueblock
MOVr0,#5;generatevalueforx
ADRr4,x;getaddressforx
STRr0,[r4];storex
ADRr4,c;getaddressforc
LDRr0,[r4];getvalueofc
ADRr4,d;getaddressford
LDRr1,[r4];getvalueofd
ADDr0,r0,r1;computey
ADRr4,y;getaddressfory
STRr0,[r4];storey
Bafter;brancharoundfalseblock
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If statement, contd.
;falseblock
fblockADRr4,c;getaddressforc
LDRr0,[r4];getvalueofc
ADRr4,d;getaddressford
LDRr1,[r4];getvalueford
SUBr0,r0,r1;computeab
ADRr4,x;getaddressforx
STRr0,[r4];storevalueofx
after...

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Example: Conditional
instruction implementation
;trueblock
MOVLTr0,#5;generatevalueforx
ADRLTr4,x;getaddressforx
STRLTr0,[r4];storex
ADRLTr4,c;getaddressforc
LDRLTr0,[r4];getvalueofc
ADRLTr4,d;getaddressford
LDRLTr1,[r4];getvalueofd
ADDLTr0,r0,r1;computey
ADRLTr4,y;getaddressfory
STRLTr0,[r4];storey
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Example: switch statement

C:
switch(test){case0:break;case1:}

Assembler:
ADRr2,test;getaddressfortest
LDRr0,[r2];loadvaluefortest
ADRr1,switchtab;loadaddressforswitchtable
LDRr1,[r1,r0,LSL#2];indexswitchtable
switchtabDCDcase0
DCDcase1
...
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Example: FIR filter

C:
for(i=0,f=0;i<N;i++)
f=f+c[i]*x[i];

Assembler
;loopinitiationcode
MOVr0,#0;user0forI
MOVr8,#0;useseparateindexforarrays
ADRr2,N;getaddressforN
LDRr1,[r2];getvalueofN
MOVr2,#0;user2forf
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FIR filter, cont.d

ADRr3,c;loadr3withbaseofc
ADRr5,x;loadr5withbaseofx
;loopbody
loopLDRr4,[r3,r8];getc[i]
LDRr6,[r5,r8];getx[i]
MULr4,r4,r6;computec[i]*x[i]
ADDr2,r2,r4;addintorunningsum
ADDr8,r8,#4;addonewordoffsettoarrayindex
ADDr0,r0,#1;add1toi
CMPr0,r1;exit?
BLTloop;ifi<N,continue
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ARM subroutine linkage

Branch and link instruction:
BLfoo
Copies current PC to r14.

To return from subroutine:

MOV r15,r14

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Nested subroutine calls

Nesting/recursion requires coding
convention:
f1

LDRr0,[r13];loadargintor0fromstack
;callf2()
STRr13!,[r14];storef1sreturnadrs
STRr13!,[r0];storeargtof2onstack
BLf2;branchandlinktof2
;returnfromf1()
SUBr13,#4;popf2sargoffstack
LDRr13!,r15;restoreregisterandreturn

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Summary
Load/store architecture
Most instructions are RISCy, operate
in single cycle.
Some multi-register operations take
longer.

All instructions can be executed

conditionally.
2008 Wayne Wolf

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