Counters

Asynchronous Counters

Synchronous Counters

1. Output of first flip flop is connected

1. No connection between the output of

to clock input of the next flip flop.

first FF and the clock input of next

And so on.

FF.

2. All FFs are not clocked

simultaneously
3. Low Speed.

2. All FFS are clocked simultaneously.

3. Faster with total propagation delay of
only one FF.

Notes On Counters

Modulus : Number of states through which the counter passes before restarting to the starting
state. Hence a 2 bit counter has 4 States also called a mod-4 counter.

3 bit counter passing through all the 8

states.

Notes On Counters
Lock-Out : When a shortened modulus counter goes into one
of its invalid states and can not come back to its normal
counting sequence that is counter gets stuck in the invalid state
then the counter is said to be in a lockout state.

Order Interchangeable
MOD- M

MOD-N

MOD-MN

Asynchronous Counters

fig : Two bit ripple up counter using

negative edge triggered flip flops.

Asynchronous Counters (Cont)

Two Bit Ripple Down Counter Using Negative Edge triggered Flip Flops

Asynchronous Counters (Cont)

M = 0 Down Counter
M = 1 Up Counter
M

CLK
FF1
K

FF2
Q

Two bit ripple up down counter using Negative Edge Triggered Flip Flops

Flip Flops (Revised)

Design Of Asynchronous Counter

Counters With Unused States

After
Puls
es

Design of a Mod-6 Asynchronous counter using T FFs

Q3

State
Q2
Q1

Design Of Asynchronous Counter (Cont)

Q2 Q1
Q3

00
0

01
0

11

R = Q3.Q2
0

10

Asynchronous Mod-6 counter using T Flip Flop

1
R

CLK

Q
CLR

FF3

FF2

FF1

Q
CLR

Q
CLR

Asynchronous Mod-10 Counter using T Flip Flop

Asynchronous Mod-10 Counter using T Flip Flop ( Cont)

Q2Q1
Q4Q3
00
01

00

01

11
10

11

10

Asynchronous Mod-10 Counter using T Flip Flop ( Cont)

3 Bit Ripple Counter Using D Flip Flop

3 Bit Ripple Counter Using D Flip Flop ( Cont )

H/W All Solved Numerical Problems

Design Of Synchronous Counters

Excitation Tables

Design Of Synchronous Counters ( Cont )

1. Determine Number Of Flip Flops Required.

2. Draw State Diagram.
3. Choose the desired flip flop and its excitation table.
4. Minimise expression for excitations.
5. Draw the logic diagram.

Design Of Synchronous 3 Bit Up Counter

1. Number Of Flip Flops Required = 3
2. Draw The state diagram :

Design Of Synchronous 3 Bit Up Counter ( Cont )

3. Select the type of flip flop : JK Flip Flop and write its excitation table :
Presen
t State
Q3
Q2
Q1

Next
State
Q3
Q2
Q1

Required
Excitations
J3
J2
J1

K3
K2
K1

0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X

Design Of Synchronous 3 Bit Up Counter ( Cont )

4.

J3 = m(3) + d(4,5,6,7)
K3 = m(7) + d(0,1,2,3)
J2 = m(1,5) + d(2,3,6,7)
K2 = m(3,7) + d(0,1,4,5)
J1 = m(0,2,4,6) + d(1,3,5,7)
K1 = m(1,3,5,7) + d(0,2,4,6)

J3 = Q2.Q1
K1 = 1

K3 = Q2.Q1

J2 = Q1

K2 = Q1

J1 = 1

Design Of Synchronous 3 Bit Up Counter ( Cont )

J3

K3
CLK

Q3

J2

K2

Q2

J1

K1

Q1

Design Of Synchronous 3 Bit Up/Down Counter

Design Of Synchronous 3 Bit Up/Down Counter ( Cont )

Design Of Synchronous 3 Bit Up/Down Counter ( Cont )

J3 = Q2.Q1.M + Q2.Q1.M
K3 = Q2.Q1.M + Q2.Q1.M
J2 = Q1.M+ Q1.M
K2 = Q1.M + Q1.M
J1 = 1
K1 = 1

Design Of Synchronous 3 Bit Up/Down Counter ( Cont )

M

J3

K3
CLK

Q3

J2

K2

Q2

J1

K1

Q1

Design Of Synchronous Modulo-8 Gray Code Counter

Design Of Synchronous Modulo-8 Gray Code Counter ( Cont )

TC

TB

TA

Design Of Synchronous Modulo-8 Gray Code Counter ( Cont )

Design Of Synchronous Modulo-8 Gray Code Counter ( Cont )

J3

K3
CLK

Q3

J2

K2

Q2

J1

K1

Q1

Synchronous BCD Counter

Synchronous BCD Counter ( Cont )

Synchronous BCD Counter ( Cont )

Synchronous BCD Counter ( Cont )

JA = QB.QC.QD
KA = Q D
JB = QC.QD
KB = QA.QD
JC = Q D
KC = QC.QD
JA = 1
KA = 1

Others Counters

1. Johnson Counter ( Twisted Ring Counter )

2. Ring Counter

End