Beruflich Dokumente
Kultur Dokumente
T
TM
1L
TM
TM
Processor Modes
TM
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
spsr
Banked
Banked
out
Registers
Registers
User
FIQ
IRQ
SVC
Undef
Abort
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
TM
TM
Changing mode on an
Exception
There are total 37
registers in the
register file,of those,
20 registers are
hidden from a program
at user mode. These
registers are called
banked registers
TM
Interrupt Masks
Interrupt masks are used to stop specific interrupt requests from
interrupting the processor.
There are two interrupt request levels available on the ARM
processor coreinterrupt request (IRQ) and fast interrupt request
(FIQ).
The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which
control the masking of IRQ and FIQ, respectively.
The I bit masks IRQ when set to binary 1, and similarly the F bit
masks FIQ when set to binary 1.
TM
Processor Modes
TM
Condition Flags
Condition flags are updated by comparisons and the result of ALU operations
that specify the S instruction suffix.
For example, if a SUBS subtract instruction results in a register value of zero,
then the Z flag in the cpsr is set. This particular subtract instruction specifically
updates the cpsr.
TM
10
10
PIPELINE
TM
11
11
PIPELINE
In the first cycle the core fetches the ADD instruction from memory.
In the second cycle the core fetches the SUB instruction and decodes the
ADD instruction.
In the third cycle, both the SUB and ADD instructions are moved along
the pipeline.
The ADD instruction is executed, the SUB instruction is decoded, and
the CMP instruction is fetched. This procedure is called filling the
pipeline.
The pipeline allows the core to execute an instruction every cycle.
39v10 The ARM Architecture
TM
12
12
PIPELINE EXECUTION
TM
13
13
EXCEPTIONS/INTERRUPTS
Reset vector is the location of the first instruction executed by the processor
when power is applied.
Data abort vector is similar to a prefetch abort but is raised when an instruction
attempts to access data memory without the correct access permissions.
Fast interrupt request vector is similar to the interrupt request but is reserved
for hardware requiring faster response times.
TM
14
14
TM
15
15
Core Extensions
The hardware extensions are standard components placed next to the ARM core.
They improve performance, manage resources, and provide extra functionality and
are designed to provide flexibility in handling particular applications.
There are three hardware extensions ARM wraps around the core:
Cache and tightly coupled memory (TCM)
Memory management
Coprocessor interface.
TM
16
16
The cache is a block of fast memory placed between main memory and the
core
ARM has two forms of cache. The first is found attached to the Von
Neumannstyle cores. It combines both data and instruction into a single
unified cache, as shown in figure
TM
17
17
TM
18
18
MEMORY MANAGEMENT
TM
19
19
COPROCESSORS
TM
20
20
T
TM
21L
DATA PROCESSING
INSTRUCTIONS
They are
Move instructions
Arithmetic instructions
Logical instructions
Comparison instructions
Multiplyinstructions
Most data processing instructions can process one of their operands using
the barrel shifter.
TM
22
22
Move Instructions
TM
23
23
Move Instructions
Barrel Shifter
TM
24
24
Move Instructions
Barrel shifter operations
TM
25
25
Move Instructions
Logical shift left by one.
TM
26
26
TM
27
27
Arithmetic Instructions
The arithmetic instructions implement addition and subtraction of
32-bit signed and unsigned values.
TM
28
28
Arithmetic Instructions
Example 1
Example 2
TM
29
29
Arithmetic Instructions
Example 3
TM
30
30
TM
31
31
Logical Instructions
Logical instructions perform bitwise logical operations on
the two source registers
Example 1
TM
32
32
Logical Instructions
Example 2
TM
33
33
Comparison Instructions
TM
34
34
Comparison Instructions
Example
TM
35
35
Multiply Instructions
The multiply instructions multiply the contents of a pair of registers
and, depending upon the instruction, accumulate the results in with
another register. The long multiplies accumulate onto a pair of
registers representing a 64-bit value. The final result is placed in a
destination register or a pair of registers
TM
36
36
Multiply Instructions
TM
37
37
Multiply Instructions
Example 1
TM
38
38
Multiply Instructions
Example 2
TM
39
39
Branch Instructions
Example 1
TM
40
40
Example 2
TM
41
41
Load-Store Instructions
Load-store instructions transfer data between memory and
processor registers. There are three types of load-store instructions:
single-register transfer
multiple-register transfer,
swap.
TM
42
42
Load-Store Instructions
TM
43
43
Load-Store Instructions
Example 1
TM
44
44
Single-Register Load-Store
Addressing Modes
TM
45
45
Single-Register Load-Store
Addressing Modes
Example 1
TM
46
46
Multiple-Register Transfer
Load-store multiple instructions can transfer multiple registers between memory and
the processor in a single instruction. The transfer occurs from a base address register
Rn pointing into memory. Multiple-register transfer instructions are more efficient
from single-register transfers for moving blocks of data around memory
TM
47
47
Multiple-Register Transfer
TM
48
48
Multiple-Register Transfer
TM
49
49
Multiple-Register Transfer
TM
50
50
Multiple-Register Transfer
TM
51
51
Stack Operations
TM
52
52
Stack Operations
When you use a full stack (F), the stack pointer sp points to an address that is
the last used or full location (i.e., sp points to the last item on the stack).
TM
53
53
Stack Operations
TM
54
54
Swap Instruction
TM
55
55
Swap Instruction
Example 1
TM
56
56
Example 1
TM
57
57
TM
58
58
TM
59
59
Coprocessor Instructions
TM
60
60
The count leading zeros instruction counts the number of zeros between
the most significant bit and the first bit set to 1.
TM
61
61
TM
62
62
Exception Priorities
TM
63
63
Interrupts
TM
64
64
TM
65
65
A VIC based interrupt service routine shows how the vector interrupt
controller (VIC) changes the design of an interrupt service routine.
TM
66
66
TM
67
67
TM
68
68
TM
69
69
TM
70
70
TM
71
71
TM
72
72
TM
73
73