Instructor

Dr. Richard Gale

ADC0820 8 bit A/D

Converter Test Results
Chandrakanth Renduchintala
Carlos De Niz

ECE - 5366

Fall 2013
1

Performed Tests
Continuity
Leakage
IIH
IIL
Power Consumption
Dynamic

Tests

INL
DNL
Skew Added during Test Plan presentation

Test Equipment & Software

NI PXI System
-Lab VIEW
- 4130 (1nA resolution)
- 4141 (10 pA resolution)
- 2515

Switch Executive
JMP Statistical Analysis
Wave Generators

20 Mhz Rigol (DG1022)

50 Mhz Keithley (3390)

Agilent Mixed Signal Oscilloscope - 2.5 Ghz

(MSO9254A)
GW Power Supply (GPC-3030D)
Precision SourceMeter Keithley (2410)

Continuity Test - Procedure

Ground all the pins, source or sink a current of

100A through each pin to test for the ESD diode,
and measure the voltage.
Read the voltage measured by source meter and
store the value
Repeat the same procedure for all the digital pins

Continuity Test (Source) Front

Panel

Data Analysis Continuity (Source)

All digital pins, D0-D7,

have a similar histogram.
See appendix

Data Analysis Continuity (Source)

Cp and Cpk are greater

than the expected values
(Cp>2 and Cpk> 1.5)

Continuity Test (Sink) Front

Panel

Data Analysis Continuity (Sink)

The data presents a bimodal

distribution which is not critical due to
the small difference among
measurements ~0.004 V
See additional data in the appendix

Data Analysis Continuity (Sink)

Cp and Cpk are

greater than the
expected values
(Cp>2 and Cpk>
1.5)

10

Power Consumption

Connect 5V to Vcc
Connect GND
After obtaining the current, the power is calculated as:
P = Vcc * Icc

11

Data Analysis Supply Current (Icc)

Typical Supply Current

(Icc)= 7.5mA
12

Data Analysis - Power

Power = 5V
* Icc
13

Leakage Current

Power up the device

Set input pin to VIL level
IIL is measured by forcing VIL voltage on a pin and reading
value of current through the pin. This is done for all input pins.
Set input pin to VIH level
IIH is measured by forcing VIH voltage on a pin and reading
value of current through the pin. This is done for all input pins.

Condition
VIL = 0.4V, VIH =
5.0V

14

Front Panel - IIH

15

Data Analysis Leakage Current IIH

16

Data Analysis Leakage Current IIH

17

Front Panel - IIL

18

Data Analysis Leakage Current IIL

19

Data Analysis Leakage Current IIL

20

Dynamic Tests

21

Dynamic Tests - Schematic

0-5V

To the
Logic
Analyzer

5V

NC

To the
Logic
Analyzer

5V

CLK Fcn
Gen
Conversion
Ready Pin

5V

22

DNL and INL

DNL is defined as the maximum deviation from one LSB

between two consecutive levels, over the entire transfer
function

INL is the max deviation from the ideal TF (best fit line) to
the actual TF, expressed in % or in LSBs
Vref (+) = 5V; Vref (-) = GND; LSB = 5/256 = 19.53mV

23

DNL

DNL = (V(k) V(k-1) )/

24

INL

INL = Error between ideal and

measured/LSB

25

Transfer Function (0~2.5V)

26

Transfer Function (2.5~5V)

27

Outputs

INT
Conversio
n ready
signal

ADC
Output

28

Skew

From time markers Ax-Bx = 4

ns

29

30

References

Mixed Signal IC testing - Mark Burns & Roberts 2nd Ed

http://www.ti.com/lit/ds/symlink/adc0820-n.pdf
http://zone.ni.com/devzone/cda/epd/p/id/5949
http://zone.ni.com/devzone/cda/epd/p/id/5946
http://zone.ni.com/devzone/cda/epd/p/id/392#0requirement
s
http://www.embedded.com/design/real-time-andperformance/4007596/DSP-Tricks-A-D-converter-testingtechniques-and-finding-missing-codes-in-ADCs
http://www.ti.com/product/adc0820-n

31

Appendi
x

32

Data Analysis Continuity (Source)

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Data Analysis Continuity (Source)

34

Data Analysis Continuity (Source)

35

Data Analysis Continuity (Sink)

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Data Analysis Continuity (Sink)

37

Data Analysis Continuity (Sink)

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Continuity Test VDD

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Continuity Test VSS

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