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Domain1
Clock
Domain2
Agenda
What is Clock Domain Crossing (CDC)
The Problem ? The trend
Leads to Chip Failure .no software fix..
List of Keywords
Keyword
Meaning
CDC
Structural Check
Functional Check
Gray code
Spyglass
ip_block
sgdc
Abstract model
F
F1
F
F2
Tp
Period of repetition
(linked with its
frequency)
Phase depicts rise &
fall transitions
A flop can be triggered
thru any of clock
phases.
+ve
-ve
Phase
Domain of a clock
Logic which is triggered
by clock (or derived
clocks)
Also known as
Synchronous system.
Conversely, domains
with clocks of variable
phase and frequency are
different clock domains.
Also known as
Asynchronous.
Domain 27Mhz
Domain 100Mhz
Setup/
Hold
Why is it important?
Multiple cases of Chip failure due to this effect across the
world.
Chip Failures in past, failure Cost.
Wrong clock connections
IP data convergence issue.
st_ck
soft_reset_active_stbus
gdp_proc_clk
st_ck
ctrl_req_int
ctrl_req
11
Meta-stability
A flip-flop needs input to be stable before and after the clock edge. (Setup & Hold Time) .
In CDC crossing, there will be setup & hold violations.
Then, the output of flip-flop may take much longer time to reach a valid logic level. This is called
metastability.
Very
close
Synchronizing
clock frequency
Duration of
metastable output
(1/Tau)
data changing
frequency
14
15
Da
synchronizer
FF2
AW
FF3
As
Synchronized signal
C1
Clk
C lk
A
A W
A S
16
17
18
Actual
Chip
Killer !!
20
To avoid CDC issues, Hold the data till a time-out (using Pulse extenders).
Q1
D1
Clk1
Clk1
Counter
==N
clk2
21
clk_A
domain
clk_B
domain
Disadvantage
Delay in synchronizing control signals (in both directions) affects the
thru-put.
Logic in control path ensures that transfer on Data
bus is coherent.
22
clk_A
Domain
clk_B
Domain
Functional Checks
Formally verify that protection is error free.
Functional CDC
(assertion based)
Structural
CDC
1
24
25
CDC OK on RTL
Can we assume Silicon will work ?
26
27
Physical View
Huge delay
imbalance
100 ns
1ns
Not Checked
In flow
Capture Period : 5 ns
1ns
Capture Period : 5 ns
Related Issues
Shoot-thru with-in a clock domain
data_in
clock
dout_out
clk
clk
Shoot Thru
may occur if
capture clock
is delayed
clock2
VHDL: Due
to Delta
Delay
In Verilog NonBlocking can
trigger new events
31
How to avoid ?
Glitch
across CDC paths
33
Agenda
Glitch in CDC
Impact of Glitch in Asynchronous circuits
Recommendations to avoid glitch in CDC
Different approaches to run CDC checks on SOC
Solution to CDC problems - SpyGlass tool
How Spyglass tool works?
Conclusion
34
Glitch in CDC
Glitch is an un-wanted pulse, mostly created
when multiple signals converge thru. Combo
logic
STA is not applicable to asynchronous interfaces
Expected o/p : Constant Low
Actual o/p : Low-High-Low
35
Ck1
Ck1
Ck2
Ck2
Ck1
36
qualifier
qualifier
Ck1
Ck1
Ck2
Ck2
37
38
39
Top_Block
40
41
42
43
List of Keywords
Keyword
Meaning
CDC
Structural Check
Functional Check
Gray code
Spyglass
ip_block
sgdc
Abstract model
References
[1] William J. Dally and John W. Poulton, Digital Systems Engineering,
Cambridge University Press, 1998
[2] Mark Litterick, Pragmatic Simulation-Based Verification of Clock Domain
Crossing Signals and Jitter Using SystemVerilog Assertions, DVCon 2006
www.verilab.com/files/sva_cdc_paper_dvcon2006.pdf
[3] Clifford E. Cummings, Clock Domain Crossing (CDC) Design &
VerificationTechniques Using SystemVerilog, SNUG-2008, Boston.
[4] Atrenta Spyglass,
http://www.atrenta.com/solutions/spyglass-family/spyglass.htm
45
Thanks
Thanks to DCG IP & SoC team
to discuss various issue and for
partnership in different projects
CDC analysis.
APPENDIX
Why ?
Non-blocking assignment can trigger additional events in the
same time step.
module dut(rst_n,clock,clock_half,enb,sig_b);
input rst_n, clock, clock_half, enb;
output sig_b;
reg sig_a;
reg sig_b;
49
50
Forward
path
Reverse
path
51
Reset Synchronization
Asynchronous resets must be de-asserted synchronously
Asynchronous de-assertion of resets may put the design into an
unintended state
asynchronous reset de-assertion in reset
reset
o_reset
F2
F3
reset de-assertion is
synchronized and happens in
o_reset after two clock edges
clk_B
reset
network
Reset Synchronizer
reset asserted asynchronously in
both reset and o_reset together
clk_B
reset
o_reset
52
Little's Formula
At steady state, the same number of processes are arriving in a
queue as are leaving the queue.
In this case, Little's formula applies:
n= W
where:
n = the average queue length
W = the average wait time
= the average arrival rate of processes
If one knows two of the above variables, one can compute the third.