D FLIP FLOP DESIGN

AND
CHARACTERIZATION

-BY
LAKSHMI SRAVANTHI KOUTHA

What is a Flip Flop?

Flip Flop is a circuit that change states depending on the control
signal and it is also the basic storage element in sequential logic
Wikipedia

D FLIP FLOP TRUTH TABLE

CLOCK

Qnext

Rising edge

Rising edge

Non-Rising

D FF SCHEMATIC

Source: Wikipedia

D FF SCHEMATIC

TOOL USED:

CADENCE VIRTUOSO
(GlobalFoundaries 180nm CMOS Technology)

REQUIREMENTS:

5 TWO-INPUT NAND GATES

1 THREE-INPUT NAND GATE

2-INPUT NAND GATE

3-INPUT NAND GATE

W/L RATIO:

W/L

PMOS

NMOS

600nm

400nm

180nm

180nm

D FF SYMBOL

FF TEST BENCH

SCHEMATIC OUTPUT

FF LAYOUT

2-INPUT NAND GATE LAYOUT

3-INPUT NAND GATE LAYOUT

PMOS TRANSISTOR
LAYOUT

NMOS TRANSISTOR
LAYOUT

FF LAYOUT OUTPUT RESPONSE

Some definitions of parameters:

Power Dissipation: Power is rate of energy transfer. Power
dissipation is a measure of the rate at which energy is lost.
Propagation Delay: Time required by the system to travel from
the input of a gate to the output.
Rise Time: The time required for a pulse to rise from 10% to
90% of its steady value.
Fall Time: The time taken for the amplitude of a pulse to
decrease from 90% to 10% of the maximum value.
Setup Time: The minimum time the data should be steady
before the clock event.
Hold Time: Minimum time the data signal should be held steady
after the clock event.
(All definitions used are from Wiki)

POWER DISSIPATION CALCULATION

CALCULATION OF OTHER PARAMETERS

COMPARISON OF SCHEMATIC AND LAYOUT

SCHEMATIC

LAYOUT

COMPARISON OF SCHEMATIC AND LAYOUT

SCHEMATIC

LAYOUT

COMPARISON OF SCHEMATIC AND LAYOUT

SCHEMATIC

LAYOUT

COMPARISON OF SCHEMATIC AND LAYOUT

SCHEMATIC

LAYOUT

SCHEMATIC PARAMETERS
Temp(C)

Power

Prop

Rise time

Fall time

Setup

Hold time

-100

3.137

71

40.3

29.1

5.1

-50

3.21

81.7

50.4

36.3

5.1

-25

3.18

87.2

55.1

39.7

5.1

3.22

93

59.9

43.67

5.1

27

3.34

99.6

64.9

47.8

5.1

50

3.17

105.1

68.6

51.4

5.1

75

3.26

111.13

72.6

55.8

5.1

100

3.36

117.6

76.8

60

5.1

150

3.52

131

84.68

69.6

5.1

200

3.66

146.7

93.99

79

5.1

250

3.85

168.2

102.3

92.2

5.1

300

4.25

208.2

115.24

112.8

5.1

diss in W

delay in ps in ps

in ps

time in ps

in ps

LAYOUT PARAMETERS
Temp(C)

Power diss Prop

in W

Rise time

delay in ps in ps

Fall time

Setup

Hold time

-200

3.04

137.69

79.06

76.4

4.997

-100

3.51

218.05

149.86

121.8

4.997

-50

3.67

256.12

184.3

146.8

4.997

-25

3.65

275.67

200.44

159.3

4.997

3.83

295.44

216.08

173.2

4.997

25

3.994

316.94

231.35

188.6

4.997

50

4.184

335.45

244.35

202

4.997

100

4.301

376.66

276.01

240.2

4.997

150

4.48

420.74

297.13

266.7

4.997

200

4.865

472

323.07

306.6

4.997

250

5.225

541.99

352.9

357.9

4.997

in ps

time in ps

in ps

ERROR DISPLAYED

CONT(ERROR DISPLAYED)

CONT(ERROR DISPLAYED)

CONT(ERROR DISPLAYED)

CONCLUSION:

The schematic of the flip flop shows normal range for the parameters
calculated, but has unstable results for very low and very high
temperature. Temperature range is -25C to 200C.
The layout also exhibits the same similarity in the calculations but
results in unstable outputs. Temperature range is 0C to 150C.

REFERENCES:
http://www.ohio.edu/people/starzykj/webcad/ee415/VLSI/design/sizing/trans_si
ze.htm
http://ece451web.groups.et.byu.net/cadence-help/tutA2.html#calc
http://ece451web.groups.et.byu.net/cadence-help/cadTOmat.html
http://ece451web.groups.et.byu.net/cadence-help/index.html
Wikipedia.org
http://www.falstad.com/circuit/e-edgedff.html
http://www.ece.ucsb.edu/Faculty/Johnson/ECE152A/L6%20-%20Latches,
%20the%20D%20Flip-Flop%20and%20Counter%20Design.pdf
http://www.ittc.ku.edu/~yangyi/5%20Delay.pdf

THANK YOU!!!