A9130 MFS introduction

MCG/MRD/TOS

2006.11

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Architecture(1)
Page 2
G G G G G G S S G G G G G G
P P P P P P S S P P P P P P
WW

S
M
M

S
M
M

G G G G G O S S O G G G G G
P P P P P M S S M P P P P P
C WWC
P
P

E E E E E E M M E E E E E E
1 1 1 1 1 1 U U 1 1 1 1 1 1
X X

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Architecture(2)
Page 3

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Architecture(3)
Page 4

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Glossary
Page 5
ATCA: Advanced Telecom Computing Architecture
E1: Primary rate or aggregate bandwidth transmissions conforming to
ITU
GP: GPRS Processing
LIU: Line Interface Unit
MFS: Multi-BSS Fast packet Server
NE: Network Element
OMCP: O&M Control Processing
PCU: Packet Control Unit
PDU: Power Distribution Unit
ShMC: Shelf Management Controller board
SMM: Shelf Management Modules
SSW: Switch Gigabit Ethernet
TP: Transmission Processing

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Dimension and Weight

Page 6

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Boards Allocation(1)
Page 7
Boards allocation for the main ATCA
shelf.

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Boards Allocation(2)
Page 8
Boards allocation for the extension ATCA shelf

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Power systemPower Distribution Unit(1)

Page 9
The JSXPDU consists of two independent branches, the BATA and BATB.

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Power systemPower Distribution Unit(2)

Page 10
JSXPDU Front View

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Power systemCooling
Page 11
Shelf Airflow
Usually the cooling system runs the fans at 40%.

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ATCA Shelf
Page 12

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ATCA subrack front and back views

Page 13

ATCA subrack front view.

2006.11

ATCA subrack back view.

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ATACOMCP board
It provides the following features:

Page 14

A Pentium M processor with up to 1.8 GHz speed

Up to 4 GByte main memory SDRAM with ECC protection
Redundant ATCA Base interface
Two USB 2.0 interfaces on the front plate
60 GByte hard disk
Support for Carrier Grade Linux Ed. 3.1
On-board IPMC compliant to IPMI V.1.5 with redundant IPMB support
Different Rear Transition Modules (RTM) available separately
A CMC module providing two serial interfaces on the front plate.

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ATACOMCP Front Plate

Page 15

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ATACJBXOMCP LEDs(1)
Page 16

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ATACJBXOMCP LEDs(2)
Page 17

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ATACJBXOMCP Key
Page 18

On pressing the reset key, a hard

reset is triggered and all attached onboard devices are reset.

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ATACJBXOMCP Front Plate Connectors

Two mini USB 2.0 connectors on its front plate.
These interfaces are not used for MFS application.

2006.11

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ATACJBXSSW
It provides the following features:

Page 20

Advanced TCA compliant switch

Managed 24-port Layer 2 Gigabit switch for the base interface
Gigabit Ethernet support for 14 payload slots
Eight base and one fabric Gigabit Ethernet uplinks via the rear
transition module
16-port Layer 2 Gigabit Ethernet switch for the fabric interface
ATCA Management Controller (IPMI version 1.5) which
communicates with Shelf Management controllers
SNMP agent for switch management
Option for TDM clock generation and synchronization via CGM
module
Designed for NEBS level 3 and ETSI requirements.

2006.11

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ATACJBXSSW Front plate

Page 21

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ATACJBXSSW LEDs(1)
Page 22

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ATACJBXSSW LEDs(2)
Page 23

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ATACJBXSSW LEDs(3)
Page 24

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ATACJBXSSW Base Interface LEDs

Page 25

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ATACJBXSSW Connectors
Page 26

The front plate provides the following connectors:

RJ-45, which is used for debugging only
Serial, which is used for factory settings.

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ATACJBXSSW Reset Key

Page 27

A reset of all on-board I/O devices and the CPU is performed when the reset
key is set to the active position. The reset is maintained until the key is returned
to the inactive position, however at least 200 ms are guaranteed by a local
timer.

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ATACJAXSSW
Page 28

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ATACJAXSSW LEDs
Page 29

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ATACJBXGPU
The JBXGPU board is installed in
the MFS equipment designed to
handle the General Packet Radio
Service (GPRS) in the BSS.

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Page 30

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ATACJBXGPU Architecture
The JBXGPU can be split into eight functional modules :

Page 31

The OBC module, based on the Puma-Agx PrPMC and the JGXDBC EPLD,
provides processing power for GPRS packet handling.
The HDLC Termination module ensures management of the Frame Relay low
layers for the Gb and GSL interfaces
The DSP module provides processing power for the management of the Ater
interface low layers
The TDM Termination module provides the physical termination of the 16 E1
interfaces of the board (Ater or Gb) interfaces and a spatial and temporal
switch
The IPMC module provides the IPMB interface for hardware management
Services
The Ethernet switch module provides a switch between data and control
Ethernet frames
The NE1OE module provides emission/reception of the E1 links over Ethernet
The Power Supply module provides all of the required on-board power supply.

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ATACJBXGPU LEDs
Page 32

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ATACJAXSMM
Page 33

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ATACJAXSMM LED
Page 34

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ATACJAXPC
Page 35

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ATACJAXPC front panel and LEDs

Page 36

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ATACJBXPS front plate and LEDs

Page 37

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ATACJBXFAN front plate and LEDs

Page 38

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ATACJBXFILL and JAXFILL

Page 39
Front/rear unused
slots are covered
with front/rear fillers

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JSXLIU shelf
Page 40

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JSXLIU shelf
Page 41

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Data flow(1/4)
Page 42
External E1 Links

O&M + TELECOM

E1 Termination Shelf

GP P
OMCPP

GP N

OMCPW

GP 1
Off-the-shelf - Common
In-house - Common
In-house - Specific

NE1oE

SSWW
SSWP

2006.11

1 Gigabit Ethernet - ATCA Base Interface

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Data flow (2/4)

Page 43

NE1OE : N E1 Over Ethernet

NE1OE provides the transport of the E1 links payload over a Giga Ethernet link
between LIU shelf (256 E1 Mux board) and JBXGPU. This transport between
board is made through a Giga Ethernet switch (SSW board)

NE1OE traffic path (E1 payload path):

JBXGPUSSWJBXMUXJBXLIUPCM Cable
PCM Cable JBXLIU JBXMUX SSW JBXGPU

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Data flow(3/4)
Page 44

L
I .
.
U .

..
.

..
.
E1

L
I .
.
U .

..
.

E
S
D

RGMII

nE1oE

SSWP

OMCP

M
A
C

M
A
C

Master/slave logic

E
S
D

16 E1 LIU
board

E1 Shelf

2006.11

..
.

256 E1 Mux

..
.
16 E1
serial
links

nE1oE

10 / 10 0 / 1G B -T
T ra n s c e iv e r

E1

16 E1
serial
links

10 / 10 0 / 1G B -T
T ra n sc e iv e r

16 E1 LIU
board

SSWW

MxGPU or TPGSM
Local
Ethernet
Switch

RGMII

256 E1 Mux
10/100/1G-BT
Ethernet Links

RGMII

nE1oE

E
E
SE
..
S
. DDS
16 E1 D

..
.

FRAMER

Serial links

aTCA chassis

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Data flow (4/4)

Page 45

E1 termination are separate from GPU processing. All GPs are connected to the E1
boards, via the SSW board (transparently).
Of course E1 boards are managed by OMCP, including the configuration of the
board. It consists mainly to provide the mapping between E1 virtual links of the
GPUs and E1 physical links of E1 boards to establish Ethernet path for each E1
between E1 boards and GP boards.

The E1 flow is just routed through the E1 boards and E1 alarms will be raised by the
framers of the GPs in a transparent way. Clock information is also to be provided
to E1 boards.

The E1/GP mapping is a semi-static mapping, since it is defined in a profil available

in a secured partition of the OMCP and exploited when the active OMCP starts-up.

A default profile will be delivered by MFS that can be updated during the
commissioning phase.

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Synchronize mode
Page 46
Autonomous Timing Mode
Free Run Mode
Centralized Timing Mode

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O&M software architecture

Page 47

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MFS Agents and processes

Page 48

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Page 49

www.alcatel-sbell.com.c

2006.11

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