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INTRODUCTION AND
ARCHITECTURE
ARM HISTORY
ARM HISTORY
ARM
ARM
3com
Agilent Technologies
Altera
Epson
Freescale
Fijitsu
NEC
Nokia
Intel
IBM
Microsoft
o
o
o
o
o
o
o
o
o
o
o
Motorola
Panasonic
Qualcomm
Sharp
Sanyo
Sun Microsystems
Sony
Symbian
Texas Instruments
Toshiba
Wipro
CISC
Compiler
Compiler
Code Generation
Processor
Greater
Complexity
Greater
Complexity
Code Generation
Processor
Instructions
Pipelines
Registers
Load Store Architecture
Instructions
Pipelines
Registers
LDR
STR
EMBEDDED SYSTEM
SOFTWARE
Application
Operating System
Hardware
ARM PROCESSOR
FUNDAMENTALS
r0r0
r1r1
r2r2
r3r3
r4r4
r5r5
r6r6
r7r7
r8r8
r9r9
r10
r10
r11
r11
r12
r12
r13
r13(sp)
(sp)
r14
r14(lr)
(lr)
r15
r15(pc)
(pc)
cpsr
cpsr
spsr
spsr
FIQ
FIQ
IRQ
IRQ
SVC
SVC
Undef
Abort
r8
r9
r10
r11
r12
r13
r13(sp)
(sp)
r14
r14(lr)
(lr)
r8
r8
r9
r9
r10
r10
r11
r11
r12
r12
r13
r13 (sp)
(sp)
r14
r14 (lr)
(lr)
r13
r13 (sp)
(sp)
r14
r14 (lr)
(lr)
r13
r13 (sp)
(sp)
r14
r14 (lr)
(lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
spsr
spsr
spsr
REGISTER ORGANIZATION
SUMMARY
User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
FIQ
User
mode
r0-r7,
r15,
and
cpsr
IRQ
User
mode
r0-r12,
r15,
and
cpsr
SVC
User
mode
r0-r12,
r15,
and
cpsr
Undef
User
mode
r0-r12,
r15,
and
cpsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
Thumb state
Low registers
Thumb state
High registers
cpsr
THE REGISTERS
Day 1
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
CPSR
SPSR
Flags
30
29
28
NZCV
Function
Condition
Flags
Status
Control
Extension
7
I F T Mode
Interrupt
Masks
Processor
Mode
Thumb State
PROCESSOR MODES
Determines which registers are active and
the access rights to the cpsr register itself
Privileged & Nonprivileged
Abort
Fast
Interrupt Request
Interrupt Request
Supervisor
System
Undefined
User
Privilege
d
Nonprivileg
ed
BANKED REGISTERS
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 sp
r14 lr
r15 pc
cpsr
-
Banked Registers
Fast
Interrup
t
Request
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
spsr_fiq
Interrup
SupervisoUndefined
t
r
Request
Abort
r13_irq
r14_irq
r13_svc
r14_svc
r13_undef
r14_undef
r13_abt
r14_abt
spsr_irq
spsr_svc
spsr_undef
spsr_abt
BANKED REGISTERS
CHANGING MODE ON AN
EXCEPTION
User
Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 sp
r14 lr
r15 pc
cpsr
-
Interrup
t
Request
Mode
r13_irq
r14_irq
spsr_irq
PROCESSOR MODE
Mode
Abbr:
Privileged
Mode[4:0]
Abort
abt
yes
10111
fiq
yes
10001
Interrupt Request
irq
yes
10010
Supervisor
svc
yes
10011
System
sys
yes
11111
Undefined
und
yes
11011
User
usr
no
10000
PROCESSOR MODES
User
FIQ
IRQ
Interrupt Routines
Thumb
(cpsr T = 1)
Instruction Size
32 bit
16 bit
Core Instruction
58
30
Conditional Execution
Most
No direct access
Register Usage
15 GPR + PC
8 bit
Core Instruction
INTERRUPT MASKS
CONDITION FLAGS
Flag
Flag Name
Set when
Saturation
oVerflow
Carry
Zero
Negative
CONDITION FLAGS
Fields
Bit 31
Flags
30
29
28
Status
27
24
00100 0
Function
nzCvq
Control
Extension
7
0 1 0 10011
i
cpsr = nzCvqjiFt_SVC
svc
CONDITION CODES
Suffix
EQ
NE
CS/HS
CC/LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Description
Equal
Not equal
Unsigned higher or same
Unsigned lower
Minus
Positive or Zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Greater or equal
Less than
Greater than
Less than or equal
Always
Flags tested
Z=1
Z=0
C=1
C=0
N=1
N=0
V=1
V=0
C=1 & Z=0
C=0 or Z=1
N=V
N!=V
Z=0 & N=V
Z=1 or N=!V
CPSR
31
28
N Z C V
24
23
16 15
I F T
mode
r15
pc
Rn
Rd
Resul
t
Rm
Barrel Shifter
MAC
N
ALU
Address Register
Incrementer
Address
Acc
PIPELINE
Decode
Execute
PIPELINED INSTRUCTION
SEQUENCE
Fetch
Cycle
Time
1
Cycle
2
Cycle
3
ADD
Decod
e
SUB
ADD
CMP
SUB
Execute
ADD
cpsr
Decod
e
Execut
e
MSR IFt_SVC
cpsr
IFt_SVC
ADD
MSR
AND
ADD
MSR iFt_SVC
SUB
AND
ADD
cpsr
PIPELINE CHARACTERISTICS
ThumbARM
decompress
FETCH
ARM decode
Reg Select
Reg
Shift
Read
DECODE
Reg
Write
ALU
EXECUTE
ARM9TDMI
Instruction
Fetch
FETCH
ARM or Thumb
Inst Decode
Reg
Reg
Decode
Read
DECODE
Shift + ALU
EXECUTE
Memory
Access
MEMORY
Reg
Write
WRITE
FETCH
ARM or
Thumb
Instruction
Decode
Reg Read
Memory
Access
EXECUTE
MEMORY
ARM11
Fetch
1
Fetch
2
Decode
Issue
Reg
Write
Multiply
Add
Multiply
DECODE
ISSUE
Shift + ALU
Shift
ALU
Saturate
MAC
1
MAC
2
MAC
3
Address
Data
Cache
1
Data
Cache
2
Write
back
WRITE
ARM EXCEPTIONS
Exceptions
VECTOR ADDRESSES
Exception / Interrupt
Shorthand
Address
High Address
Reset
RESET
0x00000000
0xffff0000
Undefined Instruction
UNDEF
0x00000004
0xffff0004
Software Interrupt
SWI
0x00000008
0xffff0008
Prefetch Abort
PABT
0x0000000C
0xffff000C
Data Abort
DABT
0x000000010
0xffff0010
Reserved
0x000000014
0xffff0014
Interrupt Request
IRQ
0x000000018
0xffff0018
FIQ
0x00000001C
0xffff001C
EXCEPTION HANDLING
0x1C FIQ
0x18 IRQ
0x14 (Reserved)
0x10 Data Abort
0x0C Prefetch Abort
0x08 Software Interrupt
0x04 Undefined Instruction
0x00 Reset
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family devices
EXCEPTION PRIORITIES
1.
2.
3.
4.
5.
6.
CORE EXTENSIONS
CACHES
MEMORY MANAGEMENT
COPROCESSORS
Coprocessors can be attached to the ARM processor
A separate chip, that performs lot of calculations for
the microprocessor, relieving the CPU some of its
work and thus enhancing overall speed of system.
A secondary processor used to speed up operation by
taking over a specific part of main processors work.
The ARM processor uses coprocessor 15 registers to
control cache, TCMs, and memory management
DESCRIPTION OF CPSR
Parts
Bits
Architecture Description
Mode
T
I&F
J
Q
V
C
Z
N
4:0
5
7:6
24
27
28
29
30
31
all
ARMv4T
all
ARMv5TEJ
ARMv5T
E
all
all
all
all
processor mode
Thumb state
interrupt masks
Jazelle state
condition flag
condition flag
condition flag
condition flag
condition flag
ARM9
ARM10
ARM11
three-stage five-stage
six-stage
eight-stage
80
150
260
335
0.06 mW/MHz
0.19 mW/MHz0. 5 mW/MHz0.4
mW/MHz
(+ cache)
(+
(+
0.97
1.1
1.3
1.2
cache)
cache)
Von Neumann
Harvard
Harvard
Harvard
8 x 32
8 x 32
16 x 32
16 x 32
ARCHITECTURE REVISIONS
RevisionExample core ISA
Implementatioenhancement
ARMv1
First ARM Processor
nARM1
ARMv2
ARM2
ARMv2a
ARM3
ARMv3
ARM6 &
ARM7DI
ARMv3M
ARMv4
ARM7M
StrongARM
26 bit addressing
32 bit multiplier
32 bit coprocessor
On chip cache
support
Atomic swap instruction
32 bit addressing
Separate cpsr & spsr
New modes UNDEF,
MMU support virtual memory
ABORT
Signed & unsigned long
multiply
Load store instruction
New Mode - System
ARCHITECTURE REVISIONS
RevisionExample core ISA
Implementatioenhancement
ARMv4T n
ARM7TDMI &
Thumb
ARMv5T
E
ARMv5T
EJ
ARMv6
ARM9T
ARM9E & ARM10E Superset of the ARMv4T
Extra inst. added for changing
state between ARM & Thumb
Enhanced multiply instructions
Extra DSP type instructions
Faster multiply accumulate
ARM7EJ &
Java acceleration
ARM926EJ
ARM11
New multimedia instructions
ARM PROCESSORS
ARM7 Family
ARM7EJ-S
ARM7TDMI
ARM7TDMI-S
ARM720T
ARM9/9E Families
ARM920T
ARM922T
ARM926EJ-S
ARM940T
ARM946E-S
ARM966E-S
ARM968E-S
Vector Floating Point Families
VFP10
ARM10 Family
ARM1020E
ARM1022E
ARM1026EJ-S
ARM11 Family
ARM1136J-S
ARM1136JF-S
ARM1156T2(F)-S
ARM1176JZ(F)-S
ARM11 MPCore
Cortex Family
Cortex-A8
Cortex-M1
Cortex-M3
Cortex-R4
Other Processors/Microarchitectures
StrongARM (DEC-Intel)
Xscale (Intel- Marvell Tech)
Other
CORTEX FAMILY
ARM Cortex-R4(F)
SWITCHING STATES
ARM to Thumb
Thumb to ARM