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B. Vasu Dev
vasu@easyarm.com
AGENDA
ARM Introduction
ARM INTRODUCTION
What is ARM?
The ARM is a 32-bit reduced instruction set
computer (RISC) instruction set architecture (ISA)
developed by ARM Holdings.
ARM also known as Advance RISC Machine
Why ARM?
Simplicity is the key philosophy behind the ARM design
RISC machine with small instruction set and consequently a small gate count.
High Performance
Low power consumption
Small amount of silicon die area.
Open Source Development Tools
Where is ARM?
History
Founded in November 1990
Spun out of Acorn Computers
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductor partners who
fabricate and sell to their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the
ARM architecture
Software tools, boards, debug hardware, application
software, bus architectures, peripherals etc
Embedded
Cores
Secure Cores
ARM720T
ARM7EJ-S
SecureCore
SC100
ARM920T
ARM7TDMI
SecureCore
SC110
ARM922T
ARM7TDMI-S
SecurCore
SC200
ARM926EJ-S
ARM946E-S
SecurCore
SC210
ARM1020E
ARM966E-S
ARM1022
ARM968E-S
ARM1026EJ-S
ARM996HS
ARM11 MPCore
ARM1026EJ-S
ARM1136J(F)-S
ARM1156T2(F)-S
ARM1176JZ(F)-S
ARM Cortex-M0
ARM Cortex-A8
ARM Cortex-M1
Development of the
ARM Architecture
1
2
3
Early ARM
architectures
Halfword
and signed
halfword /
byte support
System
mode
CLZ
SA-110
SA-1110
Thumb
instruction
set
ARM7TDMI
ARM720T
Improved
ARM/Thumb
Interworking
4T
ARM9TDMI
ARM940T
Saturated maths
DSP multiplyaccumulate
instructions
ARM1020E
5
T
E
Jazelle
ARM9EJ-S
5
T
E
ARM926EJ-S
J
ARM7EJ-S
ARM1026EJ-S
Java bytecode
execution
SIMD Instructions
Multi-processing
XScale
V6 Memory
architecture (VMSA)
ARM9E-S
ARM966E-S
Unaligned data
support
ARM1136EJ-S
ARM CORTEX
The ARM Cortex family includes processors based on the three distinct profiles
of the ARMv7 architecture.
The A profile for sophisticated, high-end applications running open and
complex operating systems
The R profile for real-time systems
The M profile optimized for cost-sensitive and microcontroller applications
Enabling the ARM Learning in INDIA
Processor Modes
Register R13-R15 having special function within the
Cortex CPU.
Registers
Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Disable interrupts (if appropriate)
Stores the return address in LR_<mode>
Sets PC to vector address
To return, exception handler needs to:
Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
Enabling the ARM Learning in INDIA
Exception Handling
The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by
exerting higher priority. It also supports dynamic reprioritisation of interrupts. Priority levels can be
changed by software during run time.
Instruction Set
Instruction Set
ARMs implement two types of instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
ARM (32bit) IS
ARM (32bit) IS
Every ARM (32 bit) instruction is conditionally executed.
The top four bits are ANDed with the CPSR condition codes, If they do not matched the
instruction is executed as NOP
The AL condition is used to execute the instruction irrespective of the value of the condition
code flags.
By default, data processing instructions do not affect the condition code flags but the flags
can be optionally set by using S. Ex: SUBS r1,r1,#1
Conditional Execution improves code density and performance by reducing the number of
Normal
Conditional
forward
CMP branch
r3,#0 instructions.CMP
BEQ skip
ADD r0,r1,r2
skip
r3,#0
ADDNE r0,r1,r2
Condition Codes
Each ARM (32bit) Instruction can be prefixed with any of
the following conditional code.
Condition Codes
Examples:
Set the flags, then use various condition codes
if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
Branch instructions
B Basic branch instruction used to jump forward or backward of up to 32 MB.
BL Branch and Link instruction jumps to the destination and stores a return
address in R14 (Link Register).
BX, BLX Branch, Brach Link and Exchange.
This swaps the instruction sets from ARM to THUMB and vice versa
while jumping.
BXJ Branch and change to Jazelle state.
ADC
AND
CMP
MOV
Multiply Instructions
MUL, MLA
MULL, MLAL
Word
Byte
Halfword
Signed byte load
Signed halfword load
Swap Instruction
Are also called as semaphore instructions
SWP R12, R10, [R9]
; load R12 from address R9 and
; store R10 to address R9
SWPB R3, R4, [R8]
; load byte to R3 from address R8 and
; store byte from R4 to address R8
SWP R1, R1, [R2]
; Exchange value in R1 and address in R2
Miscellaneous Inst.
Software Interrupt
Causes an exception trap to the SWI hardware vector
The SWI handler can examine the SWI number to decide what operation has
been requested.
By using the SWI mechanism, an operating system can implement a set of
privileged operations which applications running in user mode can request.
Ex. SWI #3
LPCExpresso setup
LPCExpresso setup
LPCExpresso setup
Eclipse IDE
Eclipse IDE
Debug Mode
1.
LPC1343
H/W- NGX_NXP
Hardware Features
Access
Description
Address
0x0000 to
GPIOnData
R/W
GPIOnData
R/W
0x3FFC
GPIOnDIR
R/W
0x8000
GPIOnIS
R/W
0x8004
GPIOnIBE
R/W
0x8008
GPIOnIEV
R/W
0x800C
GPIOnIE
R/W
0x8010
GPIOnRIS
0x8014
GPIOnMIS
0x3FF8
LPC1343 Timer/Counter
Access
Description
Address
TMR16B0IR
R/W
0x0000
TMR16B0TCR
R/W
0x0004
TMR16B0TC
R/W
0x0008
TMR16B0PR
R/W
Prescale register.
0x000C
TMR16B0PC
R/W
Prescale Counter
0x0010
TMR16B0MCR
R/W
0x0014
TMR16B0MR0
R/W
Match Register 0
0x0018
TMR16B0MR1
R/W
Match Register 1
0x001C
TMR16B0MR2
R/W
Match Register 2
0x0020
Enabling the ARM Learning in INDIA
Access
Description
Address
TMR16B0CCR
R/W
0x0028
TMR16B0CR0
RO
Capture Register 0
0x002C
TMR16B0EMR
R/W
0x003C
TMR16B0CTCR
R/W
0x0070
TMR16B0PWMC
R/W
0x0074
2)
2)
}
4)
4)
Name
Access
Description
U0RBR
RO
0x0000
U0THR
WO
0x0000
U0DLL
R/W
0x0000
U0DLM
R/W
0x0004
U0IER
R/W
0x0004
U0IIR
RO
Interrupt ID Register
0x0008
U0FCR
WO
0x0008
U0LCR
W/R
0x000C
U0MCR
W/R
Offset
Name
Access
Description
U0MSR
RO
0x0018
U0SCR
R/W
0x001C
U0ACR
R/W
0x0020
U0FDR
R/W
0x0028
U0TER
R/W
0x0030
U0RS485CTRL
R/W
0x004C
U0ADRMATCH
R/W
0x0050
U0RS485DLY
R/W
0x0054
Offset
Name
Access
Description
I2C0CONSET
R/W
0x0000
I2C0STAT
RO
0x0004
I2C0DAT
R/W
0x0008
I2C0ADR0
R/W
0x000C
I2C0SCLH
R/W
0x0010
I2C0SCLL
R/W
0x0014
I2C0CONCLR
WO
0x0018
I2C0MMCTRL
R/W
0x001C
I2C0ADR1
R/W
Offset
Name
Access
Description
I2C0ADR3
R/W
0x0028
I2C0DATA_BUFFER RO
0x002C
I2C0MASK0
R/W
0x0030
I2C0MASK1
R/W
0x0034
I2C0MASK2
R/W
0x0038
I2C0MASK3
R/W
0x003C
Offset
Name
Access
Description
AD0CR
R/W
0x0000
AD0GDR
R/W
0x0004
AD0INTEN
R/W
0x000C
AD0DR0
R/W
0x0010
AD0DR1
R/W
0x0014
AD0DR2
R/W
0x0018
AD0DR3
R/W
0x001C
AD0DR4
R/W
0x0020
AD0DR5
R/W
AD0DR6
R/W
Offset
Name
Access
Description
AD0DR7
R/W
0x002C
AD0STAT
RO
0x0030
Offset
adcInit()
adcRead()
Name
Access
Description
USBDevIntSt
RO
0x0000
USBDevIntEn
R/W
0x0004
USBDevIntClr
WO
0x0008
USBDevIntSet
WO
0x000C
USBCmdCode
WO
0x0010
USBCmdData
RO
0x0014
USBRxData
RO
0x0018
USBTxData
WO
0x001C
USBRxPLen
RO
Offset
Name
Access
Description
USBCtrl
R/W
USB Control
0x0028
USBDevFIQSel
WO
0x002C
Offset
Name
Access
Description
SSP0CR0
R/W
Control Register 0
0x0000
SSP0CR1
R/W
Control Register 1
0x0004
SSP0DR
R/W
Data Register
0x0008
SSP0SR
RO
Status Register
0x000C
SSP0CPSR
R/W
0x0010
SSP0IMSC
R/W
0x0014
SSP0RIS
RO
0x0018
SSP0MIS
RO
0x001C
SSP0ICR
WO
Offset