Designing Combinational

Logic circuits

Dr.N.B.Balamurugan
Associate Professor
Electronics & Communication Engineering
Department
Thiagarajar College of Engineering
Madurai-15
nbbalamurugan@tce.ed
u
9894346320

Learning Outcomes

At the end of this session, you should be able to

Study about the two port networks
List the applications of BJTs.
Tell the recent trends in VLSI Device Modeling

Switch Delay Model

Req

A
A
Rp
A

Rp

Rp
B

Rn

Rp
CL

A
Cint

A
NAND2

Rp

A
Rn

B
Rn

INV

Cint

A
CL
Rn

Rn

CL
NOR2
3

Input Pattern Effects on Delay

Delay is dependent on
the pattern of inputs
Low to high transition

Rp
A

Rp
B

Rn

both inputs go low

CL

delay is 0.69 Rp/2 CL

B
Rn
A

one input goes low

Cint

delay is 0.69 Rp CL

High to low transition

both inputs go high
delay is 0.69 2Rn CL
4

Fan-In Considerations
A

CL

C3

C2

C1

Distributed RC model
(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates
rapidly as a function of fan-in
quadratically in the worst case.
5

tp as a Function of Fan-In
1250

quadratic

tp (psec)

1000

Gates with
a fan-in
greater than
4 should be
avoided.

750

tpHL

500

tp

250

tpLH

linear

0
2

10

12

14

16

fan-in
6

tp as a Function of Fan-Out
tpNOR2

tpNAND2
tpINV

tp (psec)
2

All gates
have the
same drive
current.

10

12

14

16

Slope is a
function of
driving
strength

eff. fan-out
7

tp as a Function of Fan-In and Fan-Out

Fan-in:

quadratic due to increasing

resistance and capacitance
Fan-out: each additional fan-out gate
adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

8

Fast Complex Gates:

Design Technique 1
Transistor

sizing

as long as fan-out capacitance dominates

Progressive
InN

sizing
CL

MN

In3

M3

C3

In2

M2

C2

In1

M1

C1

Distributed RC line
M1 > M2 > M3 > > MN
(the FET closest to the
output is the smallest)
Can reduce delay by more
than 20%; decreasing gains
as technology shrinks
9

Fast Complex Gates:

Design Technique 2
Transistor

ordering

critical path
In3 1 M3

charged
CL

In2 1 M2

C2 charged

In1
M1
01

C1 charged

delay determined by time

to discharge CL, C1 and C2

critical path
01
In1
M3

CLcharged

In2 1 M2

C2 discharged

In3 1 M1

C1 discharged

delay determined by time

to discharge CL
10

Fast Complex Gates:

Design Technique 3
Alternative

logic structures

F = ABCDEFGH

11

Fast Complex Gates:

Design Technique 4
Isolating

fan-in from fan-out using

buffer insertion

CL

CL

12

Logical Effort

CL

Delay k Runit Cunit 1

Cin

p g f
p intrinsic delay (3kRunitCunit) - gate parameter f(W)
g logical effort (kRunitCunit) gate parameter f(W)
f effective fanout
Normalize everything to an inverter:
ginv =1, pinv = 1
Divide everything by inv
(everything is measured in unit delays inv)
Assume = 1.

13

Delay in a Logic Gate

Gate delay:
d=h+p
effort delay

intrinsic delay

Effort delay:
h=gf
logical
effort

effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size
14

Logical Effort
Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio
of its input capacitance to the inverter
capacitance when sized to deliver the
same current
Logical effort increases with the gate
complexity

15

Ratioed Logic

16

Ratioed Logic
VDD
Resistive
Load

VDD
Depletion
Load

RL

PDN
VSS
(a) resistive load

PMOS
Load
VSS

VT < 0

F
In1
In2
In3

VDD

F
In1
In2
In3

PDN
VSS

(b) depletion load NMOS

F
In1
In2
In3

PDN
VSS
(c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

17

Ratioed Logic
VDD
N transistors + Load

Resistive
Load

VOH = V DD

RL

VOL =
F
In1
In2
In3

RPN
RPN + RL

Assymetrical response
PDN
Static power consumption
VSS

tpL= 0.69 RLCL

18

Active Loads
VDD
Depletion
Load

VDD
PMOS
Load

VT < 0

VSS
F
In1
In2
In3

PDN

VSS
depletion load NMOS

F
In1
In2
In3

PDN

VSS
pseudo-NMOS

19

Pseudo-NMOS
VDD

F
CL

VOH = VDD (similar to complementary CMOS)

V2
k
2
OL
p V
k V
V V
------------- = ----- V

n
DD
Tn OL
DD
Tp
2
2

= V
V 1
OL
DD
T

kp
1 ------ (assuming that V = V
= V
)
T
Tn
Tp
k
n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

20

Pseudo-NMOS VTC
3.0

2.5

W/Lp = 4

Vout [V]

2.0

1.5

W/Lp = 2
1.0

0.5

W/Lp = 0.5

W/Lp = 1

W/Lp = 0.25
0.0
0.0

0.5

1.0

1.5

2.0

2.5

Vin [V]
21

Improved Loads
VDD

M1

Enable

M2

M1 >> M2

F
A

CL

Adaptive Load
22

Improved Loads (2)

VDD

M1

VDD

M2

Out
A
A
B
B

Out

PDN1

PDN2

VSS

VSS

Differential Cascode Voltage Switch Logic (DCVSL)

23

DCVSL Example

Out
Out

XOR-NXOR gate
24

DCVSL Transient Response

V olta ge [V]

2.5

AB
1.5

0.5

-0.5 0

AB
A,B

0.2

A,B

0.4
0.6
Time [ns]

0.8

1.0

25

Dynamic Logic

26

Dynamic Gate
Clk

Clk

Mp

off
Mp on

Out
In1
In2
In3

CL
PDN

1
Out
((AB)+C)

A
C
B

Clk

Me

Clk

off
Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
28

Properties of Dynamic Gates

Logic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary
CMOS)

Full swing outputs (VOL = GND and VOH = VDD)

Non-ratioed - sizing of the devices does not affect

the logic levels
Faster switching speeds

reduced load capacitance due to lower input capacitance (Cin)

reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging C L
29

Properties of Dynamic Gates

Overall power dissipation usually higher than static

CMOS
no static current path ever exists between VDD and GND
(including Psc)
no glitching
higher transition probabilities
extra load on Clk

PDN starts to work as soon as the input signals

exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)

Needs a precharge/evaluate clock

30

Issues in Dynamic Design 1:

Charge Leakage
CLK
Clk

Mp

Out
CL

A
Clk

Me

Evaluate

VOut
Precharge

Leakage sources

Dominant component is subthreshold current

31

Solution to Charge Leakage

Keeper
Clk

Mp

Mkp

CL

Out

B
Clk

Me

Same approach as level restorer for pass-transistor logic

32

Issues in Dynamic Design 2:

Charge Sharing
Clk

Mp

Out

CL

B=0
Clk

Charge stored originally on

CL is redistributed (shared)
over CL and CA leading to
reduced robustness

CA
Me

CB

33

Charge Sharing Example

Clk
A

Cc=15fF

Ca=15fF

Out
CL=50fF
!B

Cb=15fF
Cd=10fF

Clk

34

Solution to Charge Redistribution

Clk

Mp

Mkp

Clk
Out

A
B
Clk

Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)
35

Issues in Dynamic Design 3: Clock

Feedthrough
Clk

Mp

CL

B
Clk

Out

Me

Coupling between Out and

Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.

36

Other Effects
Capacitive

coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

37

Cascading Dynamic Gates

V
Clk

Mp

Clk

Mp

Out1

Me

Clk

Out2
In

In
Clk

Clk

Me

Out1

VTn
V

Out2
t

Only 0 1 transitions allowed at inputs!

38

Domino Logic
Clk
In1
In2
In3
Clk

Mp

11
10

PDN
Me

Out1

Clk
00
01

In4
In5

Clk

Mp Mkp

Out2

PDN
Me

39

Why Domino?
Clk

Ini
Inj
Clk

PDN

Ini
Inj

PDN

Ini
Inj

PDN

Ini
Inj

PDN

Like falling dominos!

40

Properties of Domino Logic

Only non-inverting logic can be implemented
Very high speed

static inverter can be skewed, only L-H transition

Input capacitance reduced smaller logical effort

41

Designing with Domino Logic

VDD

VDD
VDD

Clk

Mp

Clk
Out1

Mp

Mr
Out2

In1
In2

PDN

PDN

In4

In3

Can be eliminated!
Clk

Me

Clk

Me

Inputs = 0
during precharge
42

Footless Domino
VDD
Clk

VDD

Mp

Clk

Clk
Out2

In1
1

Mp

Out1
1
In2
1

VDD
Mp
Outn
1

0
In3

Inn

The first gate in the chain needs a foot switch

Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
43

Differential (Dual Rail) Domino

off
Mp Mkp

Clk
Out = AB

on
Mkp

Clk

Mp

!A

Out = AB

!B

B
Clk

Me

Solves the problem of non-inverting logic

44

np-CMOS
Clk
In1
In2
In3
Clk

Mp

11
10

PDN
Me

Out1

Clk

Me

In4
In5

PUN
00
01

Clk

Mp

Out2
(to PDN)

Only 0 1 transitions allowed at inputs of PDN

Only 1 0 transitions allowed at inputs of PUN
45

NORA Logic
Clk
In1
In2
In3
Clk

Mp

11
10

Out1

PDN

Clk

Me

In4
In5

PUN
00
01

Clk

Me

to other
PDNs

Mp

Out2
(to PDN)

to other
PUNs

WARNING: Very sensitive to noise!

46