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7-1. Introduction
Array logic
7-2. Random-Access
Memory
A memory unit stores binary information in groups of bits called
words.
1 byte = 8 bits
1 word = 2 bytes
Content of a memory
1.
2.
3.
1.
2.
Read/Write = 1
DataOut Mem[Address];
Read/Write =0
Mem[Address] DataIn;
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10
Types of memories
Types of memories
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Static RAM
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Reading
To read the contents of the memory cell stored in the loop, the transistors M5
and M6 must be turned on. when they receive voltage to their gates from the
word line WL ,they become conductive and so the Q and Q values get
transmitted to the bit line BL and to its complement BL(BAR). Finally this
values get amplified at the end of the bit lines.
Writing
The writing process is similar, the difference is that now the new value that we
want to store in the memory cell is driven into the bit line and into its
complement . Next transistors M5 and M6 are open by driving a logic one
(voltage high) into the word line connecting the bit lines to the loop. There are
two possible cases: If the value of the loop is the same as the new value driven,
there is no change.
If the value of the loop is different from the new value driven there are two
conflicting values, in order for the voltage in the bit lines to overwrite the
output of the inverters, the size of the M5 and M6 transistors must be larger
than that of the M1-M4 transistors to allow more current to flow through them
and tip the voltage in the new value direction, the loop will then amplify it to
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full rail.
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Dynamic RAM
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Dynamic RAM
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Types of memories
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4X4 RAM
kx2k decoder.
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Coincident decoding
address
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Address multiplexing
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Address multiplexing
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Construction of ROM
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0 no connection
1 connection
Address 3 = 10110010 is permanent storage using fuse link
X : means connection
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Combinational circuit
implementation
Example
Design a combinational circuit using a ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of
the input number.
Derive truth table first
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Example
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Types of ROMs
1.
2.
3.
4.
Combinational PLDs
Combinational PLDs
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PLA
F1 = AB+AC+ABC
F2 = (AC+BC)
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Programming Table
1.
2.
3.
4.
Simplification of PLA
Example 7-2
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = (0, 1, 2, 4)
F2(A, B, C) = (0, 5, 6, 7)
The two functions are simplified in the maps of Fig.7-15
1 elements
0 elements
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PLA implementation
AB
AC
BC
ABC
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PAL
Example
w(A, B, C, D) = (2, 12, 13)
x(A, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = (1, 2, 8, 12, 13)
Simplifying the four functions as following Boolean functions:
w = ABC + ABCD
x = A + BCD
y= AB + CD + BD
z = ABC + ABCD + ACD + ABCD = w + ACD + ABCD
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PAL Table
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PAL implementation
w
A
x
B
y
C
z
D
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Sequential Programmable
Devices
1.
2.
3.
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FPLS
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SPLD
Macrocell
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CPLD
CPLD
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Gate Array
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FPGA
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