Simulators

Classification of Simulators
Logic Simulators

HDL-based

Emulator-based Schematic-based

Event-driven Cycle-based

Gate

System

Classification of Simulators
HDL-based:
HDL-based Design and testbench described using HDL
Event-driven.
Cycle-based.

Schematic-based:
Schematic-based Design is entered graphically using a
schematic editor
Emulators:
Emulators Design is mapped into FPGA hardware for
prototype simulation. Used to perform hardware/software
co-simulation.

Simulation Time
The simulator models time this is called simulation time.
Simulation time is an integral multiple of the resolution limit.
The simulator cannot measure time delays less than the
resolution limit.
For gate-level simulations the resolution limit may be quite fine,
possibly down to 1ps.
For RTL simulations, there is no need to specify a fine resolution since
we are only interested in clock-cycle by clock-cycle behaviour and the
transfer functions are described with zero delay or unit delay. In this
case, a resolution limit of 1ns is usually used.

Simulation Cycle
Simulation alternates between two modes:
Statement Execution:
each statement is recalculated only if its sensitivity list has an event.
this creates a new value for each target signal and a time at which the
signal gets the value. This value/time pair is called a transaction and is
added to a transaction queue.
target signals are not updated during statement execution.
Event Processing
transactions for the current time are taken off the queue.
if a transaction represents a change in the value of the signal it
becomes an event, causing the signal to be updated with the new
value.
Signals are updated only at the next wait statement
A process with a sensitivity list has an implicit wait at the end of the process.
Dont mix sensitivity lists and wait statements: must have one or the other.

Transaction Queue

When a transaction is created it is added to the queue for the

scheduled time.
Each event generation phase consumes one time-steps
transactions.

Transactions
For example:
a <= '0' after 1 ns, '1' after 2 ns;
This signal assignment queues two transactions for signal a
1. value '0' and time delay of 1ns
2. value '1' and time delay of 2ns

Zero-Delay Transactions
It is also possible to have a zero-delay assignment:
a <= '0';
the signal is still not updated immediately,
BUT, a transaction still needs to be scheduled
If the transaction were scheduled at the current time:
It could be put at the start of the transaction queue.
It could be put at the end of the transaction queue (easier to
program)
Therefore the exact behaviour would depend on the simulator .

Delta Time
Zero-delay transactions are a problem how do you handle a
transaction for the current time?
Answer: dont! Schedule them for one delta time later
a delta time is infinitesimally small.

Each event generation phase consumes one delta time-steps

transactions.

Event-Driven Simulation Model

Example to illustrate the two-phase simulation cycle using delta
time:

Initial State

Initial Transaction Queue

After One Delta

Transaction processing phase:

Initially sum1 is 0, so this transaction represents a change from 0 1
This is therefore an event and so sum1 is updated to 1
Initially c1 is 0, so this does not represent a change no event is generated.
the transaction list for this delta is discarded.
Statement Execution Phase:
all assignments with inputs that have events get recalculated:
sum2 <= sum1 xor c;
c2 <= sum1 and c;
this creates new transactions for sum2 and c2.

After Two Deltas

Transaction processing phase:

Initially sum2 is 0, so this transaction represents a change from 01
This is therefore an event and so sum2 is updated to 1.
Initially c2 is 0, so this does not represent a change no event is generated
the transaction list for this delta is discarded
Statement Execution Phase
all assignments with inputs that have events get recalculated:
sum <= sum2;
this creates a new transaction for sum.

After Three Deltas

Transaction processing phase:

Initially sum is 0, so this transaction represents a change from 01
This is therefore an event and so sum is updated to 1.
the transaction list for this delta is discarded.
Statement Execution Phase
there are no statements triggered by this, so delta processing has
finished and simulation time can move on.

Transaction Summary
This shows all the transactions that occurred

Cycle Based Simulator

Motivation:
Advanced todays technologies
Large circuit densities.
Large verification time
Time to market

Need for faster simulators.

New innovation and techniques.
Cycle based simulation

Motivation
Advanced todays technologies
Large circuit densities
Large verification time
Time to market

Need for faster simulators

New innovation and techniques
Cycle based simulation

Cycle Simulation
Cycle simulation is a technique for simulating circuits that do not take into account the detailed circuit timing.
Cycle simulation computes the steady state response of the circuit at each clock cycle boundary.
Computes steady state response of the circuit.
-- At each cycle.
-- At each boundary node.

L
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s

Boundary Node
Internal Node

L
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Synchronous circuit: state elements change value on active edge of

clock.
Only boundary nodes are evaluated.

Cycle Simulation Techniques

Event ordering and delayed evaluation
All scheduled evaluations will take place at active edge
of clock.
All events are put in an event order which eliminate
unnecessary evaluations.

Cycle Simulation Specifications

Ignore timing and reducing the state set(2 value and
sometime 4 value)
Efficient evaluation and faster simulation

Circuit levelization at compile time.

Each element is evaluated once during clock cycle.

Simple data structure for simulator.

10 to 100 times performance over event driven simulation.

Areas of Application
Large synthesizable or logic optimizable designs.
Designs that are mostly synchronous.
Designs meet the cycle simulation subset
RTL regression ( process for estimating the relationships
among variables)
Gate-level verification.

Cycle-based versus Event-driven

Cycle-based:
Only boundary nodes
No delay information

Event-driven:
Each internal node
Need scheduling and
functions may be
evaluated multiple
times

Cycle-based is 10x-100x faster than event-driven (and

less memory usage)
Cycle-based does not detect glitches and setup/hold
time violations, while event-driven does

VHDL Delay Models

Delay is created by scheduling a signal assignment for a future time.
Delay in a VHDL cycle can be of several types
Inertial
Transport
Delta

Inertial Delay
Default delay type.
Allows for user specified delay.
Absorbs pulses of shorter duration than the specified delay.

Transport Delay
Must be explicitly specified by user.
Allows for user specified delay.
Passes all input transitions with delay.

Delta Delay
Delta delay needed to provide support
for concurrent
operations with zero delay
The order of execution for components with zero delay is not
clear

Scheduling of zero delay devices requires

the delta
delay
A delta delay is necessary if no other delay is specified
A delta delay does not advance simulator time
One delta delay is an infinitesimal amount of time
The delta is a scheduling device to ensure repeatability

Example Delta Delay