ECOE 560

Design Methodologies and Tools for

Software/Hardware Systems
Serdar Taran

Spring 2006

Outline of todays lecture

What is a software/hardware (embedded) system?

Examples
Characteristics
The design problem

Course outline
Design automation methodologies and tools
Levels of abstraction in design descriptions

ECOE 560, Spring

Definition

Embedded system: any device that includes a

programmable computer but is not itself a generalpurpose computer.
Take advantage of application characteristics to optimize
the design:

dont need all the general-purpose bells and whistles.

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Examples

Personal digital assistant (PDA).

Printer.
Cell phone.
Automobile: engine, brakes, dash, etc.
Television.
Household appliances.
PC keyboard (scans keys).

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Example: BMW 850i brake and stability control system

Anti-lock brake system (ABS): pumps brakes to reduce

skidding.
Automatic stability control (ASC+T): controls engine to
improve stability.
ABS and ASC+T communicate.

ABS was introduced first---needed to interface to existing ABS

module.

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BMW 850i, contd.

sensor

sensor

brake

brake
ABS

hydraulic
pump

brake

brake

sensor

sensor
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Characteristics of embedded systems

Sophisticated functionality.
Real-time operation.
Low manufacturing cost.
Low power.
Designed to tight deadlines by small teams.

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Functional complexity

Often have to run sophisticated algorithms or multiple

algorithms.

Cell phone, laser printer.

Often provide sophisticated user interfaces.

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Real-time operation

Must finish operations by deadlines.

Hard real time: missing deadline causes failure.

Soft real time: missing deadline results in degraded
performance.

Many systems are multi-rate: must handle operations at

widely varying rates.

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Non-functional requirements

Many embedded systems are mass-market items that

must have low manufacturing costs.

Power consumption is critical in battery-powered

devices.

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Limited memory, microprocessor power, etc.

Excessive power consumption increases system cost even in

wall-powered devices.

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Design teams

Often designed by a small team of designers.

Often must meet tight deadlines.

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6 month market window is common.

Cant miss back-to-school window for calculator.

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Example: HP DesignJet drafting plotter

Plots up to 36 inches wide at 300 DPI.

Combines a variety of tasks:

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host communication;
graphics language interpretation;
rasterization;
device control.

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The plotting process

HP-GL/2

PostScript
rasterizer

raster memory
plotter
controller

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ECOE 560, Spring

Design considerations

Memory utilization is important.

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36 inches x large x 300 DPI x n bits/pixel is a lot of memory.

Requires clever algorithms to minimize raster memory
requirements.

Requires real-time control.

Requires concurrency: read new data, rasterize, control
print head.

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HP DesignJet hardware architecture

i960KA

EEPROM

swath
RAM

pen
ctrl
ASIC

servo
proc.
(8052)
front panel

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stepper
motor

carriage
PC board

adrs
latch

1 MB
ROM

bus
if

2 MB
DRAM

proc.
support
ASIC
DRAM
ctrl

||
if
RS422

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Early architectural decisions

Chose Intel 80960KA as main processor.

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Handled parsing, rasterization control, print engine control.

Multiplexed bus reduced pin count.
Could be upgraded to floating-point if necessary.

Used modular I/O to host system.

Did not use disk for local storage.

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System components

2 MB RAM (SIMM sockets for more).

Three ASICs:

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pen interface;
processor support;
carriage.

Servo processing performed by 8052 microcontroller.

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Rasterization

Plot is generated in swaths.

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Separate swath memory.

Pixels are generated in row order by main processor.

Pixels are fed to pens in column order.
Pen interface ASIC transforms row order to column
order.

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Data flows
parsing and rasterization
i960KA

swath generation
EEPROM
servo
proc.
(8052)
front panel

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pen
ctrl
ASIC

swath
RAM

drawing

stepper
motor

carriage
PC board

adrs
latch

1 MB
ROM

bus
if

2 MB
DRAM

proc.
support
ASIC
DRAM
ctrl

||
if
RS422

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Operations

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Servo processor controls stepper motor.

Carriage processor must write, read pen alignment
marks.
Processor support ASIC provides multiple functions:
interrupt and mailbox communication.
Motion controller decodes position of print carriage and
paper; watchdogs servo.

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Pen interface ASIC

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Interfaces to i960 bus, swath memory, carriage ASIC.

Pen interface reads pixels from swath in predetermined
pattern using pixel address generator.
Must support bidirectional printing since head prints both
ways.

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Carriage ASIC

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Interfaces to carriage processor bus, pen interface ASIC,

servo controller.
Reads timing control registers using the CPU bus.
Delay registers add correction for pen alignment.

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Development process

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Pixel shuffling algorithm for pen interface/carriage ASICs

was prototyped in C.
Built emulators for ASICs to allow parallel development
of i960 software and hardware.

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Software development environment

Plotter software could be run on Unix workstation or

target platform.

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Differed in I/O and print engine subsystems.

Print engine was emulated on host with X window interface
showing swath state.

Used in-house RTOS.

HP-GL/2 parser was legacy code.

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Software development environment, contd.

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Rewrote vector/raster converter from assembly language

to C to port to i960.
Used gdb960 as monitor debugger on target system,
communicating with host.
Front panel developed on PC, tested by user interface
designers, marketing.
Paper loading designed by mechanical engineers.

ECOE 560, Spring

Outline of todays lecture

26

What is a software/hardware (embedded) system?

Course outline
Design automation methodologies and tools
Levels of abstraction in design descriptions

ECOE 560, Spring

Course Outline

System design flow

Modeling, specifying, and representing systems:

Description languages for design specifications and implementations

Modeling formalisms: Models of computation and concurrency

Fundamentals:

Boolean algebras, functions, relations. Propositional logic, first-order logic. Temporal

logics.

Hardware implementation (component) technologies:

CPUs, ASICs, FPGAs, DSPs, IP blocks, I/O components, networks, buses, on-chip
communication networks, reconfigurable platforms.

Software implementation (component) technologies:

Operating systems, real-time operating systems, inter-process communication,

scheduling.

Analysis, verification, testing: Functionality.

Design and implementation verification. Simulation, emulation, formal verification.

Analysis, verification, testing: Performance and timing.

Timing analysis and verification of hardware and software. Performance evaluation and
estimation.

Analysis, verification, testing: Power.

Power analysis, optimization of hardware and software. Power minimization techniques.

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System partitioning, architecture exploration.

Hardware synthesis.
Software synthesis
Interface design and synthesis

ECOE 560, Spring

Outline of todays lecture

28

What is a software/hardware (embedded) system?

Course outline
Design automation methodologies and tools
Levels of abstraction in design descriptions

ECOE 560, Spring

Design methodologies

A procedure for designing a system.

Understanding your methodology helps you ensure you
didnt skip anything.
Compilers, software engineering tools, computer-aided
design (CAD) tools, etc., can be used to:

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help automate methodology steps;

keep track of the methodology itself.

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Design goals

Performance.

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Overall speed, deadlines.

Functionality and user interface.

Manufacturing cost.
Power consumption.
Other requirements (physical size, etc.)

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Complexity

Design Challenges:
Increasing Device and Context Complexity

Exponential increase in device complexityincreasing with Moores

law (or faster)!

System context in which devices are deployed (e.g. cellular radio) are
increasing in complexity as well exponential increases in design
productivity

We have exponentially more components!

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Design Challenges: Deep Submicron Effects

Smaller geometries are causing a wide variety of effects that we have largely ignored in
the past:

Cross-coupled capacitances
Signal integrity
Resistance
Inductance

DSM Effects

Design of each transistor is getting more difficult!

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Design Challenges: Heterogeneous Components

Heterogeneity

Greater diversity of on-chip elements

Processors
Software
Memory
Analog

More components doing different things!

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Design Challenges: Stronger Market Pressures

Time-to-Money

Decreasing design window

Less tolerance for design revisions

Exponentially more complex, greater design risk,

greater variety, and a smaller design window !

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Complexity

A Quadruple-Whammy

Time-to-Money

Heterogeneity

DSM Effects

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Role of CAD: Helping humans cope

Transistors

PPC603
Pentium

10M

80486

1M
68000

100K
10K

68020

68040

MIPS R4000

160
140

8086
4004

180

Pentium Pro
PPC601

80386

Intelligence
Quotient

120
8080

1K

100

100

80

10

50

1
1975

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1980

1985

1990

Processor Complexity
Avg. Human IQ

1995

ECOE 560, Spring

Outline of todays lecture

37

What is a software/hardware (embedded) system?

Course outline
Design automation methodologies and tools
Levels of abstraction in design descriptions

ECOE 560, Spring

Phases of a design flow

requirements
specification
architecture
component
design
system
integration
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Top-down vs. bottom-up

Top-down design:

Bottom-up design:

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start from most abstract description;

work to most detailed.
work from small components to big system.

Real design uses both techniques.

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Stepwise refinement

At each level of abstraction, we must:

analyze the design to determine characteristics of the current

state of the design;
refine the design to add detail.

Design: specify and enter the

design intent

Verify:
verify the
correctness of
design and
implementation

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Implement:
refine the
design
through all
phases

ECOE 560, Spring