Beruflich Dokumente
Kultur Dokumente
1
RF Receiver
Antenna
Demodulator
RF front end LO
2
Low-Noise Amplifier
First gain stage in receiver
Amplify weak signal
Significant impact on noise performance
Dominate input-referred noise of front end
NFsubsequent 1
NF frontend NFLNA
GLNA
Impedance matching
Efficient power transfer
Better noise performance
Stable circuit
3
LNA Design Consideration
Noise performance
Power transfer
Impedance matching
Power consumption
Bandwidth
Stability
Linearity
4
Noise Figure
Definition
SNRin Sin N in
NF
SNRout S out N out
As a function of device
N device G N source
NF
G N source
5
NF of Cascaded Stages
Sin/Nin Sout/Nout
G 1 , N1 , G i, N i, GK, NK,
NF1 NFi NFK
NF2 1 NF3 1 NFK 1
NF 1 NF1 1 ...
G1 G1G2 G1G2 ...GK 1
6
Simple Model of Noise in MOSFET
k
Flicker noise V ( f ) WLC f
2
g
Vg ox
Dominant at low frequency
Id Thermal noise I d2 ( f ) 4kT g m
: empirical constant
2/3 for long channel
much larger for short channel
Vi PMOS has less thermal noise
Input-inferred noise
k
Vi 2 ( f ) 4kT
g m WLCox f
7
Noise Approximation
Noise spectral
density
1/f noise
Thermal noise
dominant
Thermal noise
Frequency
Band of interest
8
Power Transfer and Impedance Matching
9
Available Power
10
Reflection Coefficient
Rs V IZ L
jXs jXL
Vs I V RL V IZ s
a
2 Rs
I I * ( Z L Z L* ) V IZ s*
Pdel b
2 2 Rs
VsVs* (V IZ s )(V IZ s )*
Pmax aa*
4 Rs 4 Rs b Z L Z s*
(V IZ s* )(V * I *Z s ) a ZL Zs
Pref Pmax Pdel bb*
4 Rs
11
Reflection Coefficient
No reflection
Maximum power transfer
12
S-Parameters
Parameters for two-port system analysis
Suitable for distributive elements
Inputs and outputs expressed in powers
Transmission coefficients
Reflection coefficients
13
S-Parameters
a1 b2
S21
S11
S22
S12
b1 a2
b1 S11a1 S12 a2
b2 S 21a1 S 22 a2
14
S-Parameters
b1 S11 input reflection coefficient with
S11 the output matched
a1 a 20
b2 S21 forward transmission gain or
S21
a1 a 20 loss
b1
S12 S12 reverse transmission or
a2 a10 isolation
b2
S22
a2 a10 S22 output reflection coefficient with
the input matched
15
S-Parameters
I1 I2
Z1 S Z2
Vs1 V1 V2 Vs2
V1 I1Z1* V2 I 2 Z 2* Re( Z1 )
S11 S21
V1 I1Z1 V V1 I1Z1 Re( Z 2 ) V
s 2 0 s 2 0
V1 I1Z1* Re( Z 2 ) V2 I 2 Z 2*
S12 S22
V2 I 2 Z 2 Re( Z1 ) V V2 I 2 Z 2 V
s 1 0 s 1 0
16
Stability Condition
Necessary condition
1 | S22 |2 | S11 |2 | S |2
K 1
2 | S12 S21 |
where S S11S22 S12 S21
Stable iff
| S |2 L L 1
where | S11 |2 | S 22 |2
L | S12 S 21 |
2
17
A First LNA Example
io Assume
Rs
No flicker noise
Vs
ro = infinity
Cgd = 0
Reasonable for appropriate
bandwidth
Rs 4kTRs Effective transconductance
io g m Z in
Gmeff
Vs Vgs Vs Rs Zin
gmVgs 4kTg
m
18
Power Gain
Voltage input
Current output
2
ii *
g m Z in
G | Gmeff |
o o 2
VsVs*
Rs Z in
2 2
g m 1 ( jC gs ) gm
Rs 1 ( jC gs ) 1 jRs C gs
2
g 2
T 1
m
1 ( Rs C gs )
2 2
Rs
19
Noise Figure Calculation
Power ratio @ output
Device noise + input-induced noise
Input-induced noise
N device G N in 4kT g m
NF 1
G N in g m2
4kTRs
1 2 ( RsC gs ) 2
1 (1 2 Rs2C gs2 )
Rs g m
2 gm
1 Rs g m T
Rs g m ( g m / C gs ) 2 C gs
20
Unity Current Gain Frequency
iout Ai
Ai
iin
iout T fT
Ai 1
TT
iin T 0dB
frequency f
21
Small-Signal Model of MOSFET
i2
i1
Cgs
V1 V2 Cgd
rds
Cdb
i1 Rg Cgd i2
Rg: Gate resistance
Cdb
Cgs Vgs ri: Channel charging
V2
V1 ri rds resistance
gmVgs
22
T Calculation
i1 Rg Cgd i2 i1 Rg Cgd i2
I1 s (Cgs C gd ) s 2 riCgsCgd
Y11
V1 V 0 1 s (Cgs Cgd ) Rg sriCgs s 2 Rg riCgsCgd
2
23
T of NMOS and PMOS
Set: 0.25um CMOS Process*
Y11 ( j T )
1
Y21 ( j T )
Solve for T
gm
T gm
Cgs C gd
25
Review of First Example
No impedance matching
Capacitive input impedance
Output not matched
Power transfer
S11=(1-sRCgs)/(1+sRCgs)
S21=2Rgm/(1+sRCgs), R=Rs=RL
Power consumption
High power for NF
High power for S21
26
Impedance Matching for LNA
Resistive termination
Series-shunt feedback
Common-gate connection
Inductor degeneration
27
Resistive Termination
io
Rs 4kT/Rs 4kT/RI 4kTgm
Vs RI Is Rs RI Vgs
gmVgs
Current-current power gain
2
gm
G
1 / Rs 1 / RI j Cgs
Noise figure
2
Rs Rs 1 1 2
NF 1 g m Rs 2
RI g m Rs RI T
28
Comparison with Previous Example
Previous example
2
NF 1 Rs g m 2
Rs g m T
Resistive-termination
2
Rs Rs 2
NF 1 1 g m Rs 2
RI g m Rs RI T
Introduced by input
resistance Signal attenuated
29
Summary - Resistive Termination
Noise performance
Low-frequency approximation
Input matched Rs = RI = R
4
NF 2
gm R
Broadband input match
Attenuate signal
Introduce noise due to RI
NF > 3 dB (best case)
30
Series-Shunt Feedback
RF Broadband matching
RL
Rs
( RF RL )(1 g m Ra sRaC gs )
Rin
Vs 1 g m ( RL Ra ) s ( Ra RF RL )C gs
Ra (1 g m Ra )( RF Rs )
Rout
1 ( g m sC gs )( Rs Ra )
sC gs ( Ra RF Rs RF Ra Rs )
Rs RF iout
1 ( g m sC gs )( Rs Ra )
RL
Cgs Vgs gmVgs Could be noisy
Vs
Ra
31
Common-Gate Structure
4kTgm
RL
Rs RL
Rs 4kTRs
Vs Vgs gmVgs
I out
Geff
Vs Rs 4kTRs RL
gm gm
32
Input Impedance of CG Structure
Input impedance
Yin=gm+sCgs
Input-impedance matching
Low frequency approximation
Direct without passive components
1/gm=Rs=50 ohm
33
Noise Performance of CG Structure
2 g m2
G Geff
(1 g m Rs ) 2 2 ( Rs Cgs ) 2
N device G N in 4kT g m
NF 1
G N in g m2
4kTRs
(1 g m Rs ) 2 2 ( RsCgs ) 2
1
Rs g m
(1 g m Rs ) 2 2 Rs2C gs2
2
1 4 2
T
Signal attenuated
34
Power Transfer of CG Structure
Rs = RL = R = 50 ohm
Z in Z s* 1 g m Rs sRsC gs
S11
Z in Z s 1 g m Rs sRsC gs
sRsC gs
2 sRsCgs
2 RL g m
S21 2 RLGeff
1 g m Rs sRsC gs
2
2 sC gs
35
Summary CG Structure
Noise performance
No extra resistive noise source
Independent of power consumption
Impedance matching
Broadband input matching
No passive components
Power consumption
gm=1/50
Power transfer
Independent of power consumption
36
Inductor Degeneration Structure
Zin
Rs Lg iout
Rs Lg
iin Cgs Vgs gmVgs
Vs Vin
Ls Vs Ls
1
Vin I in sLg I in ( I in g mVgs ) sLs
sC gs
1 1
I in sLg I in ( I in g m I in ) sLs
sC gs sC gs
1 g m Ls
I in s ( Lg Ls ) Zin
sC gs C gs
37
Input Matching for ID Structure
Zin
Rs Ls Lg iout
1 g m Ls
Zin=Rs Z in s ( Lg Ls )
sC gs C gs
1
IM{Zin}=0 2
0
( Lg Ls )C gs
g m Ls
RE{Zin}=Rs Rs
C gs
38
Effective Transconductance
Zin
Rs Ls Lg iout
I out g m ( sC gs )
Geff
Vs Rs Z in
gm
1 s ( RsC gs g m Ls ) s 2C gs ( Lg Ls )
39
Noise Factor of ID Structure
2 g m2
G Geff
[1 2C gs ( Lg Ls )]2 2 ( RsC gs g m Ls ) 2
= 0 @ 0
Calculate NF at 0
N device G N in 4kT g m
NF 1
0
G N in g m2
4kTRs 2
( RsC gs g m Ls ) 2
1 2 ( RsCgs g m Ls ) 2
Rs g m
40
Input Quality Factor of ID Structure
I R L Stored power
Q
Lost power
C
V I I * C 1
II R*
CR
Rs Ls Lg 1 1
Qin
CR C gs ( Rs g m Ls / C gs )
gmLs/Cgs Cgs 1 1
Vs
( Rs C gs g m Ls ) 2Rs C gs
41
Noise Factor of ID Structure
Increase power transfer
1 gmLs/Cgs = Rs
Qin
( RsC gs g m Ls )
Decrease NF
NF
0 gmLs/Cgs = 0
1 2 ( RsCgs g m Ls ) 2
Rs g m
Conflict between
1
1 Power transfer
Rs g m Qin2
Noise performance
42
Further Discussion on NF
Frequency @ 0
NF
0
2 ~= 1/Cgs/(Lg+Ls)
Input impedance
1 2 ( RsC gs g m Ls ) 2
Rs g m matched to Rs
1
4( g m Ls ) 2 1 RsCgs=gmLs
Rs g m C gs ( Lg Ls ) Ls Rs T
4 Ls Suitable for hand
1
Lg Ls calculation and design
Large Lg and small Ls
Ls Lg 1 02C gs
43
Power Transfer of ID Structure
Rs = RL = R = 50 ohm
Z in Z s* 1 s C gs ( Lg Ls ) sg m Ls sRsCgs
2
S11
Z in Z s 1 s 2C gs ( Lg Ls ) sg m Ls sRsCgs
1 s 2Cgs ( Lg Ls )
1 s ( g m Ls RsC gs ) s 2C gs ( Lg Ls )
2 g m RL
S 21 2Geff RL
1 s ( RsCgs g m Ls ) s 2Cgs ( Lg Ls )
1 1
@ 20 Qin
( Lg Ls )C gs ( RsC gs g m Ls )
2 g m RL R
S11 0; S 21 j 2 g m RLQin j T L
j0 ( Rs C gs g m Ls ) 0 Rs 44
Computing Av without S-Para
Rs Lg
Vs
Ls
g m2 L2 3
Cox
W
Vgs VT 2
Rs
g m Ls
gm
RsC gs
C gs 2 L C gs Ls
46
Power Consumption
L2 Rs2 1 4 Ls
P 2 3 NF 1
0 Ls (1 Lg / Ls ) 0
Lg Ls
Technology constant
L: minimum feature size
: mobility, avoid mobility saturation region
Standard specification
Rs: source impedance
0: carrier frequency
Circuit parameter
Lg, Ls: gate and source degeneration inductance
47
Summary of ID Structure
Noise performance
No resistive noise source
Large Lg
Impedance matching
Matched at carrier frequency
Applicable to wideband application, S11<-10dB
Power transfer
Narrowband
Increase with gm
Power consumption
Large Lg
48
Cascode
49
Rs Lg Vo
LL Vo
Rs Lg
Cgs Vgs gmVgs
M1
Vs Vs Ls LL
Ls
50
LNA Design Example (1)
Vdd
Lvdd Lb2 Cb2 V
out
M4 Output
Ld Lout
bias
Vbias
M2 M3
Lb1
Rs Tm
M1
Lg Lgnd
Cb1
Vs Cm
Ls
Input
bias Off-chip
matching
[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997. 51
LNA Design Example (1)
Supply
filtering Lvdd
M4 Ld Lout
Vbias
M2 M3
Lb1
Rs Tm
M1
Lg Lgnd
Cb1
Vs Cm
Ls
Unwanted
parasitics
[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997. 52
Circuit Details
Two-stage cascoded structure in 0.6 m
First stage
W1 = 403 m determined from NF
Ls accurate value, bondwire inductance
Ld = 7nH, resonating with cap at drain of M2
Second
4.6 dB gain
W3 = 200 m
53
54
LNA Design Example (2)
NF = 1 + K/gm
gm = gm1 + gm2
M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 Off-chip
M5
Cs CX matching
Off-chip M7
CB
matching M3 M6
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 55
Simplified view
56
LNA Design Example (2)
M8 M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX
M7
CB
M3 M6
Bias
feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 57
LNA Design Example (2)
M8 M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX
M7
CB
M3 M6
Bias
feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 58
LNA Design Example (2)
VA
M8 M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX
M7
CB
M3 M6
Bias
DC output = VB1 feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 59
60
LNA Design Example (3)
Objective is to design tunable RF LNA that
would:
61
LNA Architecture
The cascode architecture
provides a good input
output isolation
Transistor M2 isolates the VDD
Miller capacitance R1
Input Impedance is obtained LD
using the source M3 Matching
degeneration inductor Ls Network
R2 M2
Gate inductor Lg sets the Output to
resonant frequency Mixer
M1
The tuning granularity is Input to LNA LG
achieved by the output LS
matching network
62
Matching Network
The output matching tuning
network is composed of a
varactor and an inductor.
The LC network is used to
convert the load impedance
into the input impedance of
the subsequent stage.
A well designed matching
network allows for a maximum
power transfer to the load.
By varying the DC voltage
applied to the varactor, the
output frequency is tuned to a
different frequency.
63
Simulation Results - S11
The input return loss
S11 is less than 10dB
at a frequency range
between 1.4 GHz and
2GHz
64
Simulation results - NF
The noise figure is 1.8
dB at 1.4 GHz and rises
to 3.4 dB at 2 GHz.
Noise Figure
65
Simulation Results - S22
By controlling the voltage applied to the varactor the output frequency
is tuned by 2.5 MHz.
The output return loss at 1.77 GHz is 44.73 dB and the output return
loss at 1.7725 GHz 45.69 dB.
66
Simulation Results - S22
The output return loss at 2 GHz is 26.47 dB and the output return
loss at 1.9975 GHz 26.6 dB.
67
Simulation Results - S21
The overall gain of
the LNA is 12 dB
68
Simulation Results - Linearity
The third order input intercept is 3.16 dBm
-1 dB compression point ( the output level at which the actual gain
departs from the theoretical gain) is 12 dBm
69
From an earlier slide:
k
Flicker noise V ( f ) WLC f
2
g
Vg ox
Dominant at low frequency
Id Thermal noise I d2 ( f ) 4kT g m
: empirical constant
2/3 for long channel
much larger for short channel
Vi PMOS has less thermal noise
Input-inferred noise
k
Vi ( f ) 4kT
2
g m WLCox f
71
gdo vs gm in short channel
72
gdo vs gm in short channel
73
Fliker noise
Traps at channel/oxide interface randomly
capture/release carriers
k
V (f)
g
2
fWLCox
Kf Kf
I (f)
2
d n
f f
Parameterized by Kf and n
Provided by fab (note n 1)
Currently: Kf of PMOS << Kf of NMOS due to buried channel
To minimize: want large area (high WL)
74
Induced Gate Noise
Fluctuating channel potential couples
capacitively into the gate terminal, causing a
noise gate current
2
ing 4kTg do
2
5 T
is gate noise coefficient
Typically assumed to be 2
Correlated to drain noise!
75
real
Input impedance
1 g m Ldeg
Z in ( s ) s ( Lg Ldeg )
sC gs C gs
Set to be real and equal to source resistance:
1 g m Ldeg
2
0 Rs
( Lg Ldeg )C gs C gs
76
Output noise current
I d2 ( f ) kT g do 1 2 c d d2 (4Q 2 1)
Noise scaling factor:
1
4
1 2 c d d2 (4Q 2 1) d
gm
g do 5
Where for 0.18 process
c=-j0.55, =3, =6, gdo=2gm,
d = 0.32
1 0 ( Lg Ldeg )
Q
2 Rs0C gs 2 Rs
77
Noise factor
o g do
F 1 1 2 c d (4Q 2 1) d2
T 2Q gm
g do
K nf 1 2 c d (4Q 2 1) d2
2Q g m
Compare:
N device G N in 0
NF 1 0 4( Rs C gs ) 1
2 2
4
0
G N in Rs g m T 2Q
78
Noise factor scaling coefficient versus Q
79
Example
Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8
GHz
1
From Q
2 Rs0C gs
1 1
C gs 442 fF
2 Rs0Q 2(50)2 1.8e9(2)
Rs C gs Rs 50
Ldeg 0.17nH
gm T 2 47.8e9
1 1
2
0 Lg 2 Ldeg 17.5nH
( Lg Ldeg )C gs 0 C gs
80
Have We Chosen the Correct Bias Point?
82
Lower current density to 100
o g do 1
F 1 1 2 c d (4Q 2 1) d2
T g m 2Q
84
85
Recall
88
Differential LNA
Value of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits
89
LNA Employing Current Re-Use
F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA,
IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
91
At DC, M1 and M2 are in cascode
At AC, M1 and M2 are in cascade
S of M2 is AC shorted
Gm of M1 and M2 are multiplied.
Same biasing current in M1 & M2
LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL from the February 2004 issue.
92
IM3 components in the drain
current of the main transistor has
the required information of its
nonlinearity
Auxiliary circuit is used to tune the
magnitude and phase of IM3
components
Addition of main and auxiliary
transistor currents results in
negligible IM3 components at
output
ia g m1va g v g v 2
m2 a
3
m3 a
ib g m 3vb3
i o ia ib
Sivakumar Ganesan, Edgar Snchez-sinencio, And Jose Silva-martinez
IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006 93
MOS in weak inversion has speed problem
MOS transistor in weak inversion acts like bipolar
Bipolar available in TSMC 0.18 technology (not a parasitic BJT)
Why not using that bipolar transistor to improve linearity ?
94
Inter-stage Inductor gain boost
95
Folded cascode
Ld reduces or eliminates
Effect of Cgd1
Good fT
96
Design Procedure for Inductive
Source Degenerated LNA
Noise factor equations:
o g do 1
F 1 1 2 c d (4Q 2 1) d2
T g m 2Q
g do 1
K nf
1 2 c d (4Q 2 1) d2
g m 2Q
97
Targeted Specifications
98
Step 1: Know your process
A 0.18um CMOS Process
Process related
tox = 4.1e-9 m
= 3.9*(8.85e-12) F/m
= 3.274e-2 m^2/V.s
Vth = 0.52 V
Noise related
= gm/gdo
~ 2
~3
c = -j0.55
99
Step 2: Obtain design guide plots
100
Insights:
gdo increases all the way with current
density Iden
gm saturates when Iden larger than
120A/m
Velocity saturation, mobility degradation ----
short channel effects
Low gm/current efficiency
High linearity
deviates from long channel value (1)
with large Iden
101
Obtain design guide plots
102
Insights:
fT increases with Vod when Vod is small and
saturates after Vod > 0.3V --- short channel
effects
Cgs/W increases slowly after Vod > 0.2V
fT begins to degrade when Vod > 0.8V
gm saturates
Cgs increases
104
Design trade-offs
For fixed Iden, increasing Q will reduce the
size of transistor thus reduce total power
---- noise figure will become larger
For fixed Q, reducing Iden will reduce
power, but will increase noise factor
For large Iden, there is an optimal Q for
minimum noise factor, but power may be
too high
105
Obtain design guide plots
Linearity plots :IIP3 vs. gate overdrive and transistor size
106
Insights:
MOS transistor IIP3 only, when embedded into
actual circuit:
Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3
IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive
is not monotonic
There is a local maxima around 0.1V overdrive
107
Step 4: Estimate fT
Gm/W~0.4
109
If Q = 4, IIP3 will have enough margin:
Estimated IIP3:
IIP3(from curve) 20log(Q) = 8-12 = -4dBm
Specs require: -8 dBm
110
Q=4 and Iden = 70A/m meet the
noise factor requirement
111
Gm=0.4*128 ~ 50 mS fT = gm/(Cgs*2pi) = 48 GHz
112
Step 6: Simulation Verification
Large deviation
113
114
Comparison between targeted
specs and simulation results
115