The Instruction Execution

Instruction
Cycle
Obtain instruction from program storage
Fetch

Instruction Determine required actions and

Decode instruction size

Operand Locate and obtain operand data

Fetch

Execute Compute result value or status

Result Deposit results in storage for later use

Store

Next Determine successor instruction

Instruction
Machine Cycle:

The necessary steps carried out to perform

the operation of accessing either memory or
i/o device, constitute a machine cycle.

In a machine cycle one basic operation such

as opcode fetch, memory read, memory
write, i/o read or i/o write is performed.

An instruction cycle consists of several

machine cycles.
 Single-byte instructions require only
one machine cycle to fetch the opcode
and execute the instruction.

Two-byte and three-byte instructions

require more than one machine cycle.
The first machine cycle is required to
fetch the opcode.
The additional machine cycles are
needed to read data from or to write
data into the memory or i/o devices.
T-state:

One subdivision of an operation performed

in one clock cycle is called a state or T-
state.

The subdivisions are internal states,

synchronized with the system clock. So, one
clock cycle of the system clock is referred to
as a state.
Timing Diagram:

The necessary steps which are carried out

in a machine cycle can be represented
graphically. Such a graphical representation
is called timing diagram.
 Status signals
Machine IO/M S1 S0
cycle
Opcode 0 1 1
fetch
Memory 0 1 0
read
Memory 0 0 1
write
I/O read 1 1 0
I/O write 1 0 1
 Opcode Fetch Machine Cycle

The first step of executing any instruction is the

Opcode fetch cycle.
In this cycle, the microprocessor brings in the
instructions Opcode from memory.

The control & status signals are set as follows:

IO/M=0, s0 =1 and s1 =1.

This machine cycle has four T-states.

The 8085 uses the first 3 T-states to fetch the
opcode.
T4 is used to decode and execute it.
Timing Diagram for Opcode Fetch Machine
cycle
 Memory Read Machine Cycle
This machine cycle has three T-states.
In a memory read operation:
The 8085 places the address on the address bus

Identifies the operation as a memory read

(IO/M=0, s0=0, s1=1).

Places the contents of the memory on the data bus and

asserts the signal RD.

During the last T-state, the contents of the data bus are
read.
Timing Diagram for Memory-Read Machine
cycle
 The Memory Write Operation
In a memory write operation:
The 8085 places the address on the address bus

Identifies the operation as a memory write

(IO/M=0, s0=1, s1=0).

Places the contents of the accumulator on the data

bus and asserts the signal WR.

During the last T-state, the contents of the data bus

are saved into the memory location.
Timing Diagram for Memory-Write Machine
cycle
Timing diagram for One-Byte Instruction
(Opcode fetch cycle for MOV C, A )

13
Timing diagram for Opcode fetch cycle for MOV C, A

The Fetch Execute Sequence :

1. The p placed a 16 bit memory address
from PC (program counter) to address bus.
Figure 4: at T1
The high order address, 20H, is placed at A15 A8.
the low order address, 05H, is placed at AD7 - AD0 and
ALE is active high.
Synchronously the IO/M is in active low condition to
show it is a memory operation.
2. At T2 the active low control signal, RD, is
activated so as to activate read operation; it
is to indicate that the MPU is in fetch mode
operation.
14
Timing diagram for Opcode fetch cycle for MOV C, A

3. T3: The active low RD signal enabled

the byte instruction, 4FH, to be placed
on AD7 AD0 and transferred to the
MPU. While RD is high, the data bus
will be in high impedance mode.

4. T4: The machine code, 4FH, will then

be decoded in instruction decoder.
The content of accumulator (A) will
then copied into C register at time
state, T4.

15
 Timing Diagram for Two-byte
Instruction
To understand the memory read machine cycle, lets
study the execution of the following instruction:
MVI A, 32 2000H 3E

In memory, this instruction looks like: 2001H 32

The first byte 3EH represents the opcode for loading

a byte into the accumulator (MVI A), the second byte
is the data to be loaded.
The 8085 needs to read these two bytes from memory
before it can execute the instruction. Therefore, it will
need at least two machine cycles.
The first machine cycle is the opcode fetch
discussed earlier.
The second machine cycle is the Memory Read
Cycle.
 Timing Diagram for Two-byte
Instruction
MVI A, 32H
2000H 3EH
2001H 32H

M1 (Opcode-fetch) M2 (Memory Read)

T T T T T T T
1 2 3 4 1 2 3

A15- 20H; high-order Unspecifie 20H; High-order address

d
A8 address
00H; low- 01H; 32H;
AD7- order Add
3E; opcode
low- Data
order
AD0 Add
AL
E
Status IO/M=0,S1=1,S0=1; opcode Status IO/M=0,S1=1,S0=0; data
fetch read

RD
Timing Diagram For three-byte instruction

STA 2300H