Peripheral presentation

DMA(Direct Memory Access)

Group members :
Abeda Sultana(16)
Hosneara Ahmed(17)
Dewan Israt Jahan(49)
Farhana Siddiqua (57)
Najmun Nahar Bhuiyan(64)
3/13/17 1
 DMA
Direct memory access(DMA) is a
feature of computer systems that
allows certain hardware subsystems
to access main system
memory(RAM) independently of
thecentral processing unit (CPU)

3/13/17 2
 DMA
DMA is a method of transferring data from
the computers RAM to another part of the
computer without processing it using CPU.
While most data that is input or output from
your computer is processed by the CPU, some
data does not require processing, or can be
processed by another device. In these
situations, DMA can save processing time and
is a more efficient way to move data from the
computer's memory to other devices.

3/13/17 3
 Example of DMA
For example, a sound card may need to
access data stored in the computer's RAM,
but since it can process the data itself, it
may use DMA to bypass the CPU. Video
cards that support DMA can also access
the system memory and process graphics
without needing the CPU.Ultra DMAhard
drives use DMA to transfer data faster
than previous hard drives that required
the data to first be run through the CPU.

3/13/17 4
 Principle
A DMA controller can generatememory
addressesand initiate memory read or write cycles.
It contains severalhardware registersthat can be
written and read by the CPU.
These include a memory address register, a byte
count register, and one or more control registers.
The control registers specify the I/O port to use, the
direction of the transfer (reading from the I/O
device or writing to the I/O device), the transfer
unit (byte at a time or word at a time), and the
number of bytes to transfer in one burst.

3/13/17 5
 Basic features of DMA
The activity involved in transferring a
byte or word over the system
bus is called a bus cycle.
During bus cycle one component
must be the master which will have
complete control over the bus. Taking
control of the bus for a bus cycle is
called cycle stealing.

3/13/17 6
 Basic features of DMA
DMA is a data transfer technique
between Main Memory and External
device. It can be used to memory to
memory transfers also.
There is no involvement of
Microprocessor.
DMA controller controls the Main
Memory in the same way the
Microprocessor do.
3/13/17 7
 Basic features of DMA
Ensures very high data transfer rate.
Because the data transfer is handled
totally in hardware.
Microprocessor and DMA controller
gets control of data, address and
control bus by time sharing.

3/13/17 8
 Working Principles of DMA
DMA controller is connected with the
external device (DMA requesting I/O
device).
These activate DREQ line high for
DMA service to the controller.
After the completion of current bus
cycle the microprocessor will respond
by putting a 1 on the HLDA pin to
DMA controller.
3/13/17 9
 Working Principles of
DMA(cont.)
When the requesting device receives
this grant signal it becomes the
master.
It will remain master until it drops
signal to the HOLD pin , at which
time 8086 will drop the grant on the
HLDA pin.
After receiving HLDA, DMA controller
sends out a signal and takes the full
control of Data, Address and Control
3/13/17 10
 Working Principles of
DMA(cont.)
DMA controller puts the content of
the address register on the address
bus.
DMA controller sends a DACK signal
to the interface to tell it to put data
on data bus.
At the same time DMA controller
asserts appropriate signals to
IOR/IOW and MEMW/MEMR pins.
3/13/17 11
 Working Principles of
DMA(cont.)
Bytes of data are transferred from
the memory location indicated by the
address bus.
The address register is incremented
by 1.

The byte count register is

decremented by 1.

3/13/17 12
 Working Principles of DMA
If the byte count register is non-zero,
return to step 1 ,otherwise stop.
After completion of DMA, DMA
controller releases
a) its hold request HOLD to the
processor.
b) control of buses.
Overview of a standard DMA controller
Block Diagram of DMA controller
 DMA controller
Direct memory access (DMA) is a method that allows an
input/output (I/O) device to send or receive data directly to or
from the main memory, bypassing the CPU to speed up memory
operations. The process is managed by a chip known as a DMA
controller (DMAC).
A DMA controller is designed to service one or more I/O interfaces
and each interface is connected to the controller by a set of
conductors.
A portion of a DMA controller for servicing a single interface is
called a channel. It has n channels for n different I/O devices.
8237 has 4 channels.
Many hardware systems use DMA, includingdisk
drivecontrollers,graphics cards,network cards andsound cards.
DMA is also used for intra-chip data transfer inmulti-core
processors.
DMA controller flags and registers

A DMA controller has control and

status and temporary register.
Each channel contains
Address Registers (base and current)
Byte count register(base and count)
Mode register
Request flag
Mask flag
8086 System with 8237 DMA
controller
 Description of the parts of
8237

Mode Register: The mode register programs the

mode of operation for a channel.
Each channel has its own mode register as
selected by bit positions 1 and 0.
Bit 5 indicates whether the content of address
register are to be incremented (0) or
decremented (1) after each transfer.
Bit 4 is set 1 to enable auto-initialization.
Bit 2 & 3: Indicates the type of transfer to be
made. The three types are: verify (00),write (01)
and read (10).
6th and 7th bit of this determine the operation
mode.
 Description of the parts of
8237

Control Register: The control register programs the

control operation for each channels.
Bit 0 is set to 1 to enable memory to memory
transfer.
Bit 1 is set to 1 to held the source address
constant.
Bit 2 is used for enabling (0) and disabling (1)
controllers to accept DMA request.
Bit 4 is used to Determine whether the priority is
fixed or rotating.
Bit 6 is set 1 to indicate that DREQ is active Low.
Bit 7 is set 1 to indicate that DACK is active High.
Description of the
parts of 8237

Status register: The status

register shows status of each
DMA channel.
Lower 4 bits indicates the
states of the terminal count
of the four channels and
upper 4 bits indicates the
current presence or
absence of DMA request.

3/13/17 21
 Registers of DMA
8237(cont.)
Request Register

8-bit register used to indicate which channel is

requesting for data transfer.

Set for a channel to indicate that DREQ pin is

becoming active

Cleared when EOP(End Of Process) goes

active.

3/13/17 22
 Registers of DMA 8237(cont.)

Mask register

8-bit register used to mask a particular

channel from requesting for DMA service.

If the mask flag is set, it disables the channel

so that DMA requests are not recognized.

If a channel is not programmed for auto-

initialization, then this flag is automatically set
when EOP goes active.
3/13/17 23
 Registers of DMA 8237(cont.)
Temporary Registers

Used to hold data during memory-to-

memory transfers.

Always contains the last byte

transferred in the previous memory-
to-memory operation, unless cleared
by a Reset.

3/13/17 24
 Memory to memory
transfers

Channel 0 s current address and

count

registers are used as source

addressing and

counting
3/13/17 25
 Memory to memory transfers(cont.)

Bytes are brought in from the source

memory area into the temporary
register in 8237 and then outputting
it to destination memory area.

If destination address is incremented

or decremented as usual by setting
appropriate bits of the control
register and source address is kept
constant, same data byte is
transferred into the entire
3/13/17
destination array. 26
 Addressing of
Registers
Done via CS, IOR,IOW and A3-A0 lines
CS=0 indicates that the controller is
being accessed.
For a read IOR is Low and IOW is high.
For a write IOR is High and IOW is low.
A write to either current address or
current count register also writes to base
address or base count register.
3/13/17 27
 Addressing of Registers(cont.)

A0 = 0 : current address
register
A0 = 1 : current count register
A2-A1 : gives the channel
number
A3 = 0 : addressing address or
count register

3/13/17 28
 Other
features
Ready signal is used to extend
the bus cycles by inserting wait
states when servicing the slow
devices.

Reset signal clears the

control,status and temporary
registers and the request flags
and sets the mask flags.
3/13/17 29
 8237 operational mode
Single: A single byte (or word) is
transferred. The DMA must release
and re-acquire the bus for each
additional byte.
Block: Once the DMA acquires the
system bus, an entire block of data is
transferred.
 8237 operational
mode(cont.)
Demand: DREQ is checked after each
transfer. If inactive waits until it becomes
active and resumes the transfer. It allows
interface to stop transfer in the event
that its device cannot keep up.
Cascade: This is not a transfer mode in
this mode more than 4 channels can be
included by having a slave controller
connected to the master
 8237 DMA controller activity by
states
Between transfers the controller is in idle SI
states.
during each SI state the DREQ lines are
tested to determine if a channel is
requesting DMA transfer.
If there is an active DREQ input, HRQ is
activated and S0 state is entered.
S0 states are repeated until a HLDA signal
is returned and then a sequence of S1
through S4 occurs.
 8237 DMA controller activity by
states(cont.)
S1 may be skipped if high order byte of the
transfer address does not need to be changed.
If the device is slow, wait SW states are
inserted.
If normal timing is used, S3 states are needed.
But if compressed timing is used S3 state is
deleted.
During S4 the transfer mode is tested. Except
for incomplete block transfers in block and
demand modes, a return is made to SI.
Timing Diagram for 8237 DMA
controller