Text Book
Microelectronics Circuits
By Sedra & Smith (5th/6th Ed)
Topics
Op Amps
Ch 2
Filters
Ch 12
Oscillators
Ch 13
What is an amplifier?
Response.......Time, Frequency
Impedance.....Input, Output
Gain Transfer
Description Symbol Function
Voltage Amplifier
or Av vo/vin
Voltage Controlled Voltage Source (VCVS)
Current Amplifier
or Ai io/iin
Current Controlled Current Source (ICIS)
Transconductance Amplifier gm
or io/vin
Voltage Controlled Current Source (VCIS) (siemens)
Transresistance Amplifier rm
or vo/iin
Current Controlled Voltage Source (ICVS) (ohms)
LM111 LM324
2.1.1. The Op
Amp Terminals
terminal #1
inverting input
terminal #2
noninverting input
terminal #3
output
terminal #4
positive supply VCC
terminal #5
negative supply VEE
v3 A(v2 v1)
ideal input characteristic: infinite impedance
ideal output characteristic: zero impedance
6 4inverting
47 4 input
48
6commonmode
44 7 4 input
48 v1 vcmi vdi / 2
1 {
vcmi (v1 v2) but also... diff
2 v2 vcmi vdi / 2
1 4 4 2 4 43
noninverting input
but also...
6 4inverting
47 4 input
48
v1 vcmi vdi / 2
{
diff
v2 vcmi vdi / 2
1 4 4 2 4 43
noninverting input
Component Datasheets
Many manufacturers have made these freely
available on the internet
Example: LM 324 Operational Amplifier
dB
Decibels
Since P = V2/R
10 log (P/Pref) or 20 log (V/Vref)
In this case:
20 log (Vo/Vin) = 20 log (A) = 100
A = 105 = 100,000
Large Signal
Voltage Gain = A
Typical
A = 100 V/mV = 100V/0.001V = 100,000
Minimum
A = 25 V/mV = 25 V/0.001V = 25,000
Caution A is
Frequency
Dependent
Some
Specifications
v o = A vd
Ideal Op Amp
vo = (vd)
Open Circuit
Output Voltage
Real Op Amp
Voltage Output
Range Voltage
Positive A vd > V + vo ~ V+
Saturation
Linear Region V < A v d < vo = A vd
V+
Negative A vd < V  vo ~ V
Saturation
The voltage produced by the dependent voltage source inside the op amp
is limited by the voltage applied to the positive and negative rails.
Voltage Transfer
Characteristic
Range where
we operate
the op amp
as an
amplifier.
vd
Ideal Op Amp
Because Ri is equal
to , the voltage
across Ri is 0V.
i2 = 0
v v1 = v2
2
vd = 0 V
i1 = 0
v
1
Almost Ideal Op
Amp
Ri =
Therefore, i1 = i2 = 0A
Ro = 0
Usually, vd = 0V so v1 = v2
The op amp forces the voltage at the inverting input terminal
to be equal to the voltage at the noninverting input terminal
if there is some component connecting the output terminal to
the inverting input terminal.
Rarely is the op amp limited to V < vo < V+.
The output voltage is allowed to be as positive or as negative
as needed to force vd = 0V.
Example #1:
Voltage
Comparator
is = 0 i1 = 0
i2 = 0
is = 0 i1 = 0
i2 = 0
noninverting
input is grounded
source is applied
to inverting
Microelectronic input
Oxford University Publishing
Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.2.1.
ClosedLoop
Gain
Configuration
i1
question: what are two basic closedloop op amp
configurations which employ opamp and resistors alone?
answer:
1 i
inverting and noninverting opamp i=
note: here we examine the inverting type
0
I ( 0 / A) I 0 / A
i1
R1 R1
0 0 / A
0 i1 R2 0 I R2
A A R1
0 R2 / R1
G (2.5)
I 1 (1 R2 / R1 ) / A
2 1 0 1 1 0 / A
1 0 / A
R1 R1 1 (R2 / R1)
1
A
10
3
10
4
10
5
io .
2.2.3 Input and output Resistance of Inverting Amplifier
(not opamp)
What would happen if R1 is too small
?
R
R2
G
( R R1 )
Therefore, input resistance R1 should
be much larger than output resistance
Ideal input I I of previous stage. Unfortunately, the
resistance of i iR R1 internal resistance of most sensors are
/ R
inverting 1 I 1
large.
amplifier, not op
For high amp.
gain ( R2 / R1), we need
small R1, otherwise, R2 would be Contradictio
impractically large. n!
Solution: example
2.2
Microelectronic Circuits  Fifth Edition Sedra/Smith 50
Example 2.2:
Another
Inverting Op
Amp
Problem Statement: Consider
the circuit below...
Q(a): Derive an expression for
the closedloop gain vOut/vIn of
this circuit.
Q(b): Use this circuit to design
an inverting amplifier with gain
of 100 and input resistance of
1Mohm.
Assume that one cannot use
any resistor with resistance Figure 2.8: Circuit for Example
larger than 1Mohm. 2.2. The circled numbers
Q(c): Compare your design indicate the sequence of the
with that based on traditional
Oxford University Publishing steps in the analysis.
inverting configuration.
Microelectronic Circuits by Adel S. Sedra
(0195323033)
and Kenneth C. Smith
EXAMPLE 2.2 (a) Find 0 / I . (b) Design the inverting amplifier with
(a gain of 100 and an input resistance
0 0 1 M.
) 0
A
I I 0 I
i1
R R R
I
i2 i
R
I R
x i2 R2 0 R2 2 I
R R
0 x R2
i3
R3 R2 R3 I
R
i4 i 2 i 3 I 2 I
R R1 R3 (b input resistance 1 R1=1
0 x i4 R4 ) maximum M M
resistance in practical
circuits:
R2, R4=1 1 M
R2 R
= I I 2 I R4 gain of R =10.2 kM
R1 R R1 R3 3
100
0 R R4 R4 (If we adopt a typical inverting amplifier
2 1 and
R2=100 M, impractically large !) R1=1 M,
I R1 R2 R3
52
2.2.4. An
Important
Application
The Weighted
Summer
weighted summer  is a closedloop
amplifier configuration which provides an
output voltage which is weighted sum of
the inputs.
Figure 2.10: A
weighted summer.
iA if
iB
+
vi

Summing Amplifier
a) i1=vin/R1=1V/1k=1mA
ix=ioi2=10mA1mA=11mA
Exercise
b) i1=vin/R1=5mA
i2=i1=5mA
i2*1k= i3*1k => i3=5mA
i4=i2+i3=10mA
i5
i1
i3
+ iL
i4
V3 i1=v1/R1=v1/10k
i2=i1=v1/10mA

v3 = i2*R2= v1/10k *20k =2v1
Exercise
i5=i3+i4=v3/10k +v2/10k
i5
i1
i3
+ iL
V3
i4

Positive Feedback
node
#2
source is applied
Oxford University Publishing to noninverting
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.3 The Noninverting
2.3.1 The closeLoop Configuration
Gain
1 R
Av 1 2
R
1
R
v 1 v v This is the ideal voltage
1 R R o o
1 2 gain of the amplifier. If A
R is not >>1, there will be
1 is called the
Gain Error.
R R feedback
1 2
factor.
Gain Error is given by
GE = (ideal gain)  (actual gain)
For the noninverting amplifier,1
GE
A
1
1 A (1 A )
0 R
1 2 > 0  Input and output signals have same phase.
I R1
 Input impedance is infinite.noninverting.
 output impedance is zero.
vOut
vIn
R } R 1 (R2 / R1)
ideal gain A 1 2 : GA 1 2
R1 R1 1 1 (R2 / R1)
A
1 (R2 / R1)
nonideal gain: .G
{A
1 (R2 / R1)
vOut 1
vIn A
1 (R2 / R1) 1 (R2 / R1)
percent gainerror: pge 100
A 1 (R2 / R1) 1 1 (R2 / R1)
A
R1 1 (R2 / R1)
invertinginputpotential: .v1 vOut 1 (R / R )
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith R1 R2 1 2 1
(0195323033)
Configuration and Characteristics
of Buffer / VoltageFollower Op
Amp Configuration
vi v v vo
vo
AF 1
vi
commonmode
input
commonmode
gain
differential input
differential gain
A
CMRR 20 log10
ACm
ADi
CMMR 20 log10
ACm
v v
v1 v
i1
R1
v v0
i1
R2
v1 v v v0
R2 R1 R2
v v2
R1 R2 R2 R2
v1 v2 v2 v0
R1 R2 R R2
1
R1 R2
Difference Amplifier
R2 R2
v1 v2 v2 v0
R1 R2 R R2
1
R1 R2
R2 R2 R22
v0 v1 v2 v2
R1 R1 R2 R1 R1 R2
R2 R2 R2 R2
v0 v1
R1 R2
1 v2 v0 v2 v1
R1 R1 R1
2.4.1. A Single
OpAmp
Difference
Amp
Q: What are the characteristics of the
difference amplifier?
A: Refer to following equations
(R2 R1)R4 R2
vOut vIn2 vIn1
(R4 R3)R1 R1
R1 R 3 R2
but if then vOut vIn2 vIn1
R2 R 4
Oxford University Publishing
R1
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
A Shift in
Notation
amp (A1)
difference op
vOut = (1 +
amp (A3)
R2/R1)vIn
vOut =
non (R4/R3)vdf
inverting op
Oxford University Publishing
amp (A )
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
vIn1 vIn1 A=
10
A=
A = 10 x 25
25
vIn2 vIn2
vIn1 =
10.03V
vOut= 250 x (10.03
A = 10 x
25
10.02)V
vOut = 2.5V no
vIn2 = problem!!!
10.02V Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
differential
gain =
commonmode
gain
vOut1= 10 x 10.03 = 15V
vIn1 =
saturation
10.03V
A=
A= 25 vOut= 25 x (1515)V
10
vOut = 0V problem!!!
short
vOut1
ckt
iR1
vOut2
vIn2 vIn1
output of A1 and K vIn1 R2
A2 in terms of 1 4 4 4 22R 41 4 4 3
vOut 1vIn1iR1R2
input alone 6 4 4 4 4 4action 44 7 4 4 4 4 4 4 48
: combine terms
64 v7InDi48
vIn2 vIn1
vOut2 vOut1 (vIn2 vIn1) 2 R2
14 2 43 2R1
vInDi
2R
vOut2 vOut1 1 2 vInDi
2R1
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.4.2. The
Instrumentati
on Amplifier action: define in
terms of vdf
R4 6 4 7 4 8
step #5: Define vOut (vOut2 vOut1)
R3
output of A3.
step #6: Define gain R4 2R2
vOut 1 vdf
of revised R3 2R1
instrumentation
amplifier.
vOut R4 2R2
ADi 1
vdf R3 2R1
solution
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
Instrumentation
Amplifier
6
4
5 8
3
9
R4 R2
Ad 1 (2.21)
R3 R1
 It is usually preferable to obtain all the required
gain in the first stage. (Low Noise)
 The second stage (difference amp) is usually
designed for a gain of 1.
 We select all the secondstage resistors to be 10 2 R2
1 2 to 1000
k, practically convenient value. R1 f R1
R
A d 1 2 2 R2
R1 1 1000
R1 f
2 R2
1 2
R1 f 100 k
R1f =100.2 , R1f =100 ,
1%
R2 = 50.050 k, R2 = 49.9 k,
Microelectronic Circuits  Fifth Edition Sedra/Smith
1%
99
2.5 Effect of Finite OpenLoop Gain and Bandwidth on
A circuit designer has to be thoroughly familiar with the
Circuit characteristics of practical op
Performance
amps and the effects of such characteristics on the performance of opamp circuits.
2.5.1 Frequency Dependence of the OpenLoop Gain
A 0 b A 0b
? b , A(j ) ; (2.26) A(j ) = (2.27)
j
When A 1, t A 0 b (2.28)  ft = t/2 is specified on the data sheet as unity
t t f gain band width.
? b , A(s ) ; (2.30) A(j ) ; = t (2.31)
s f
Microelectronic Circuits  Fifth Edition Sedra/Smith
100
t f
A(j ) ; = t (2.31)
f
 If ft is known, one can easily determine the magnitude of the opamp gain at a given
The production spread in the value of ft frequency when f >> fb.
ft is preferred as a
between opamp units of the same type
specification parameter.
(part number) is much smaller than that
of A0 and fb.
 An op amp having this 6 dB/octave (=  20 dB/decade) gain roll off is said to have
a singlepole model.
A0
A( s ) (2.24) pole: s= b
1 s / b
 Since this single pole dominates the amplifier frequency response, it is called a
(for more on poles and zeros, refer to dominant pole.
Appendix E.)
2.5.2 Frequency Dependence of the ClosedLoop Gain
The effect of limited opamp gain and bandwidth on the closedloop
transfer functions.
Vo R2 / R1
We know
Vi 1 (1 R2 / R1 ) / A
A0
and A( s ) (2.24)
1 s / b
Vo ( s ) R2 / R1
Then, (2.33)
Vi ( s ) 1 R s
1 1 2
A0 R1 t /(1 R2 / R1 )
Microelectronic Circuits  Fifth Edition Sedra/Smith
101
R2 Vo ( s ) R2 / R1
for A0 ? 1 , ; (2.34) LowPass STC Network !
R1 Vi ( s ) s
1 t
t /(1 R2 / R1 ) corner frequency, 3dB (2.35)
1+R2 / R1
Vo 1 R2 / R1
We know, (2.36)
Vi 1 (1 R2 / R1 ) / A
Vo ( s ) 1 R2 / R1
Similary, ; (2.37)
Vi ( s ) s
1
t /(1 R2 / R1 )
EXAMPLE 2.4
ft = 1 MHz, find 3dB frequency of closedloop
amp with gain of 1000, 100, 10, 1, 1, 10, 100, R1
1000
R1 R2
VO 1
When R1 , R2 0, (2.39)
Vi 1 s / t
This is a lowpass STC response.
Output from capacitor of RC
Microelectronic Circuits  Fifth Edition t ) V (1 e t ) (2.40) network !
O (Sedra/Smith t
104
2.6.4 FullPower Bandwidth
I V i sin t ,
If SR < V i ,
d I
V i cos t
dt
id CMRR OS O = ?
1 M
If id =0, V 1 (0.003) 2.5V
O 1.2k
ic
o A VOS A( ) When an input signal is applied to the
CMRR
OS amplifier, the corresponding signal
output will be superimposed on the 2.5 V
ic Then the allowable signal swing at dc.
the
CMRR V/V output will be reduced.
V
OS If signal is dc, we would not know where
(another interpretation of the output is due to VOS or the signal.
CMMR)
Thus, CMRR is a measure of how * To overcome dc offset problem
total offset voltage vOS changes from
its dc value VOS when commonmode
voltage is applied.
VO I B1 R2 ; I B R2 (2.44)
How to reduce the dc output voltage due
to the input bias current
I B1 I B 2
IB : input bias current in data sheet
2
I OS I B1 I B 2 : input offset current
VO I B 2 R3 R2 ( I B1 I B 2 R3 / R1 ) (2.45)
if I B 1 I B 2 I B , VO I B R2 R3 (1 R2 / R1 )
R2 RR With this R 3 and I B1 I B 2 ,
For minimum VO , R3 1 2 (2.46)
1 R
Microelectronic Circuits R1 Sedra/Smith
2 / REdition
 Fifth 1 R2 VO I OS R2 < I B R2 (2.47)
107
Conclusion: To minimize the effect of the input
bias current,
initial
output
voltage
1
t
678
transient description (dc): .vOut (t)
RC
1 F
t0vIn(t)dt vOut (t0)
vOut 1
steadystate description (ac):
vIn sRC
1 F
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.5.2. The
Inverting
Integrator
dvIn(t)
transient description (dc): vOut (t) RFC1
dt
VOut (s)
steadystate description (ac): sRFC1
VIn(s)
Q: What is input
offset voltage (VOS)?
A: An imaginary
voltage source in
series with the
usersupplied input,
which effects an op
amp output even
when idf = 0. Figure 2.28: circuit
What will happen when model for an op amp with
short is applied?
Oxford University Publishing input offset voltage VOS.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.6.1. Offset
Voltage
dc signals cannot
pass!
internal compensation
is the presence of internal
passive components (caps)
which cause opamp to
demonstrate STC lowpass
response.
frequency compensation
Figure 2.39:
is the process of modifying
Openloop gain of a
the openloop gain. typical general
The goal is to increase purpose internally
stability Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith compensated op
(0195323033)
2.7.1: Frequency
The Dependence
gain of an internally compensated op
amp mayOpenLoop
of the be expressed as shown below
Gain
A0
transfer function in Laplace domain: A(s)
1 s/ b
A0
transfer function in frequency domain: A(j)
1 j / b
A0b
transfer function for high frequencies: A(j)
1 44 2 4 j43
b is break frequency
A0b t
magnitude gain for high frequencies: A(j)
j
unity gain occurs at t :
Oxford University Publishing
t A0b
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.7.2. Frequency
Response of
ClosedLoop VOut R2 / R1
Amplifiers VIn 1 (1 R2 / R1)/ ({A)
open
loop
gain
6 4 4inverting
44 7 op4amp
4 4 48 644 noninverting op amp
44 7 4 4 4 48
VOut R2 / R1 VOut 1 R2 / R1
VIn s 1 R2 / R1 VIn s 1 R2 / R1
1 1
t t
3dB frequency is
the frequency at
which the amplifier t
3dB
gain is attenuated 1 R2 / R1
3dB from maximum
(aka. dc ) value.
slew rate is
maximum rate of
change of an opamp slew rate (SR)
(V/us) 6 44 7 4 48
dvOut
Q: How can this be SR
dt max
problematic?
A: If slew rate is
less than rate of
change of input.
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.8.3. Slew
Rate
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