Input Output Organization

IO Interface
Modes of transfer

Interrupt

Direct Memory Access

Introduction to IO Processor
 Input or output devices attached to computer are called
Peripheral Devices
Provides an efficient mode of communication between the
central system and the outside environment
Input or Output devices attached to the computer
In the block mode edited text first stored in local memory
inside the terminal. This text is transfer to computer as a block of
data
ASCII alphanumeric characters
94 characters(26+26+10+32) that can be printed
and 34 non printing characters
Three types of control characters
Format efforts that can control layout of printing ex:
BS(Backspace),HT(Horizontal tabulation)
,CR(Carriage return)
Information separators are used to separate data
into divisions like paragraphs and pages ex:
RS(Record separator),FS (file separator)
Communication control characters are useful during
transmission of text between remote terminals ex:
STX,ETX
IO Interface

IO interface provides a method for transferring

information between internal storage and external
I/O devices.
I/O devices can not directly communicate with the
CPU due to various differences between them.
The major differences are:
1) A conversion of signal values may be required
2) A synchronization mechanism may be needed
3) Data codes and formats in peripherals differ from
the word format in the CPU and Memory
4) The operating modes of peripherals are different
from each other
Main function of IO interface circuit are data
conversion, synchronization and device selection
Each interface decodes the address and control
received from the IO bus, interprets them for
peripheral, provides signal for peripheral controller
Synchronizes data flow and supervises transfer
between peripheral and processor
I/O Bus and Interface Modules
I/O bus is attached to all peripherals.
Interface monitors the address on address bus.
If it find its own address, it activates path between
bus line and device.
All the other devices are disabled by their interfaces.
Data to read or write is made available in the data
bus.
IO command is made available in the control bus.
There are four types of IO command:
Control Command: is used to activate the peripheral and to
inform it what to do
Status Command: is used to test various status conditions in
the interface and peripheral
Output Data Command: causes the interface to respond by
transferring data from the bus into one of its registers
Input Data Command: : causes the interface to respond by
transferring data to the bus into processor registers
IO versus Memory bus

Like IO bus Memory bus also contain data, address

and control lines.
There are 3 ways in which computer buses can be
used to communicate with memory and IO.
In the first method, CPU has independent set of
buses for both memory and IO. It is done in
computers that has separate IOP and CPU.
Isolated IO

In second method computers use common bus to

transfer data between IO or memory and CPU. And
separate read and write lines.
IO read/write is enabled during IO transfer and
memory read/write is enabled during memory
transfer.
This configuration isolates all I/O interface address
with the memory address and is referred to as
Isolated IO method.
memory-mapped IO.
In third method same address space is used for both
memory and IO interface. They have only one set of
read and write signals.
No specific input or output instructions
Each interface is organized as set of registers that
respond to read and write requests in the normal
address space
It assign address for each interface which cannot be
used for memory words.
Example of IO Interface
Example of IO Interface
Example of IO Interface

A command is passed to IO device by sending a word

to appropriate interface register
control is send to control, status is send to status,
data are transferred to and from ports A and B
registers
Transfer of data, control and status information is
always via the common data bus
ASYNCHRONOUS COMMUNICATION INERFACE
ASYNCHRONOUS COMMUNICATION
INERFACE
Operation is initialized by the CPU by sending a byte to the control
register
Initialization like baud rate, no of bits, no of stop bits, parity check take
place in interface
Two bits in status register are used as flag, one for to indicate whether
transmitter register is empty, another for whether receiver register is full
CPU reads status register and check whether transmitter register is
empty
If it is empty CPU transfers a character to the transmitter register and
interface clears flag to mark register full
The first as 0 to generate start bit
The character is transferred in parallel from transmitter register to shift
register and stop bits are appended in shift register
Transmitter register is now marked empty
ASYNCHRONOUS COMMUNICATION
INERFACE
The character can now be transmitted one at a time by shifting data
in the shift register
Interface is said to be Double Buffered because a New character
can be loaded as soon as the previous one starts transmission
The receive data input is in 1 state when line is idle
Receive control monitors the receive data line for a 0 signal to
detect the occurrence of start bit
If it is detected it is transferred to shift register
Check for parity and stop bits
The character without start and stop bits is then transferred in
parallel form shift register to the receiver register
Flag set to indicate that receiver register is full
CPU reads data from the receiver register if flag is set
ASYNCHRONOUS COMMUNICATION
INERFACE
3 possible errors (in status register)
1) parity error: Even or Odd parity error
2) framing error: right number of stop bits is not
detected at the end of the received character
3) overrun error: CPU does not read the character
from the receiver register before the next one
FIFO
Modes of transfer

Data transfer between computer and IO device can

be handle in the following ways:
Programmed IO
Interrupt-Initiated IO
Direct Memory Access(DMA)
Programmed IO

Each data transfer is initiated by an instruction in

the program.
CPU stays in the program loop until IO unit indicates
it is ready for the data transfer.
It is time consuming process since it keeps processor
busy needlessly.
Example of programmed IO
The transfer of data requires three instructions:
Interrupt Initiated IO

In this type of IO, computer does not check the flag.

It continue to perform its task.
Whenever any device wants the attention, it sends
the interrupt signal to the CPU.
CPU then deviates from what it was doing, store the
return address from PC and branch to the address of
the subroutine.
There are two ways of choosing the branch address:
Vectored Interrupt
Non-vectored Interrupt

In vectored interrupt the source that interrupt the

CPU provides the branch information. This
information is called interrupt vectored.
In non-vectored interrupt, the branch address is
assigned to the fixed address in the memory.
Software Considerations
I/O routines
software routines for controlling peripherals and for
transfer of data between the processor and peripherals
I/O routines for standard peripherals are provided by
the manufacturer (Device driver, OS or BIOS)
I/O routines are usually included within the operating
system
I/O routines are usually available as operating system
procedures ( OS or BIOS function call)
Priority Interrupt

There are number of IO devices attached to the

computer.
They are all capable of generating the interrupt.
When the interrupt is generated from more than one
device, priority interrupt system is used to determine
which device is to be serviced first.
Devices with high speed transfer are given higher
priority and slow devices are given lower priority.
Establishing the priority can be done in two ways:
Using Software
Using Hardware

A pooling procedure is used to identify highest

priority in software means.
Polling Procedure

There is one common branch address for all

interrupts.
Branch address contain the code that polls the
interrupt sources in sequence. The highest priority is
tested first.
The particular service routine of the highest priority
device is served.
The disadvantage is that time required to poll them
can exceed the time to serve them in large number of
IO devices.
Using Hardware

Hardware priority system function as an overall

manager.
It accepts interrupt request and determine the
priorities.
To speed up the operation each interrupting devices
has its own interrupt vector.
No polling is required, all decision are established by
hardware priority interrupt unit.
It can be established by serial or parallel connection
of interrupt lines.
Serial or Daisy Chaining Priority.

Device with highest priority is placed first.

Device that wants the attention send the interrupt
request to the CPU.
Interrupt request line is common to all devices
If any device has its interrupt signal in low state enables
interrupt input(INT)(negative logic OR)
CPU responds to an interrupt request by enabling
INTACK
CPU then sends the INTACK signal which is applied to
PI(priority in) of the first device.
A device with PI input as 0 generates PO output as
0,meaning is that it had requested the attention, it
place its VAD(interrupt vector address) on the bus.
And it block the signal by placing 0 in PO(priority out)
If not it pass the signal to next device through
PO(priority out) by placing 1.
This process is continued until appropriate device is
found.
The device whose PI is 1 and PO is 0 is the device with
highest priority.
Parallel Priority Interrupt

It consist of interrupt register whose bits are set

separately by the interrupting devices.
Priority is established according to the position of
the bits in the register.
Mask register is used to provide facility for the
higher priority devices to interrupt when lower
priority device is being serviced or disable all lower
priority devices when higher is being serviced.
Corresponding interrupt bit and mask bit are AND
ed and applied to priority encoder.
Priority encoder generates two bits of vector address.
Another output from it sets IST(interrupt status flip
flop).
IEN can be set or reset by the program to provide an
overall control over interrupt system
INTACK enables bus buffers in the output register
and vector address VAD is placed into the data bus
Interrupt Cycle

When IEN is cleared interrupt request from IST is

neglected
IEN clears to zero every time an interrupt is
acknowledged by the processor
After instruction cycle CPU checks for IEN and IST
If both are zero it continues to next instruction cycle
If both are one it continues to interrupt cycle
Software routines
Initial and final operations
Direct Memory Access(DMA)

In DMA there is direct communication between

memory and the peripheral devices.
CPU is idle and has no control over the memory
buses.
DMA controller uses buses and transfer the data
directly between I/O devices and memory.
BR(Bus Request) signal is used by DMA controller to
request CPU for the buses.
CPU then places the address bus ,data bus and read
and write lines on the high impedance state which
behave like open circuit.
CPU then activates BG(Bus Grant) signal to
acknowledge BR signal.
DMA now has full control over the buses and
perform the transfer.
Transfer can be perform in two ways:
Burst Transfer
Cycle Stealing
In burst transfer, a number of memory word is
transfer in a continuous burst. It is done while
communicating with fast devices and cant be
stopped or slow down.
In cycle stealing, one data word is transfer at a time.
CPU delays it operation for one cycle during which
DMA transfer takes place.
DMA Controller
DMA Controller

It communicates with CPU through data bus and

control lines.
Registers in DMA are selected by CPU by enabling
DS and RS.
RD and WR signals are for read and write operation.
When BG=0 CPU can communicate with DMA
register for read or write operation.
When BG=1 DMA communicate directly with the
memory.
DMA Controller

It has three register: address, word count and control

register.
Address register contain address which specify the
location of memory to read or write.
It is incremented after each word is transferred into
memory.
Word count register holds the number of words to be
transferred.
It is decremented by one after each word is
transferred into memory and regularly check for zero.
Control Register specify the mode of transfer.
DMA is first initialized by CPU. After that DMA
continue to transfer data.
CPU initialize the DMA by sending the following
information through the data bus:
Starting address of memory block for read or write.
The word count or number of words to read or write.
Control to specify mode such as read or write.
Control to start DMA
Once DMA is initialized, CPU stop communicating
with DMA unless it receive interrupt signal or if it
wants to check how many words has been
transferred.
DMA transfer
DMA Transfer (I/O to Memory)
1) I/O Device sends a DMA request
2) DMAC activates the BR line
3) CPU responds with BG line
4) DMAC sends a DMA acknowledge to the I/O device
5) I/O device puts a word in the data bus (for memory write)
6) DMAC write a data to the address specified by Address
register
7) Decrement Word count register
8) Word count register=0,EOT interrupt
9) Word count register
DMAC checks the DMA request from I/O device
Input-Output Processor(IOP)

It is a processor with direct memory access capability

that communicates with IO devices.
IOP is similar to CPU except that it is designed to
handle the details of IO operation.
Unlike DMA which is initialized by CPU, IOP can
fetch and execute its own instructions.
IOP instruction are specially designed to handle IO
operation.
IOP
IOP

Memory occupies the central position and can

communicate with each processor by DMA.
CPU is responsible for processing data.
IOP provides the path for transfer of data between
various peripheral devices and memory.
Data formats of peripherals differ from CPU and
memory. IOP maintain such problems.
Data are transfer from IOP to memory by stealing
one memory cycle.
IOP

Instructions that are read from memory by IOP are

called commands to distinguish them from
instructions that are read by the CPU.
INTEL 8089 IOP