FET(FieldEffectTransistor)

Few important advantages of FET over conventional Transistors

1. Unipolar device i. e. operation depends on only one type of

charge carriers (h or e)
2. Voltage controlled Device (gate voltage controls drain
current)
3. Very high input impedance (109-1012 )
4. Source and drain are interchangeable in most Low-frequency
applications
5. Low Voltage Low Current Operation is possible (Low-power
consumption)
6. Less Noisy as Compared to BJT
7. No minority carrier storage (Turn off is faster)
8. Self limiting device
9. Very small in size, occupies very small space in ICs
10. Low voltage low current operation is possible in MOSFETS
11. Zero temperature drift of out put is possiblek
 Types of Field Effect Transistors
(The Classification)

JFET
n-Channel JFET
FET
MOSFET (IGFET) p-Channel JFET

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET
TheJunctionFieldEffectTransistor(JFET)

Figure:nChannelJFET.
 SYMBOLS

Drain Drain
Drain

Gate Gate
Gate

Source Source
Source

n-channel JFET n-channel JFET p-channel JFET

Offset-gate symbol
 BiasingtheJFET

Figure:nChannelJFETandBiasingCircuit.
Operation of JFET at Various Gate Bias Potentials

Figure:Thenonconductivedepletionregionbecomesbroaderwithincreasedreversebias.
(Note:ThetwogateregionsofeachFETareconnectedtoeachother.)
 Operation of a JFET

Drain
-
N

Gate
P P + +
- DC Voltage Source

-
N
+
Source
 OutputorDrain(VDID)CharacteristicsofnJFET

Figure:CircuitfordraincharacteristicsofthenchannelJFETanditsDraincharacteristics.

Nonsaturation(Ohmic)Region: V V V
DS GS P
2I V2
Thedraincurrentisgivenby I DSS V V V DS
DS V2 GS P DS 2
P
Saturation(orPinchoff)Region:
V V V
DS GS P
I 2 2
DSS V
I V V 1 GS
DS V2 GS P and I I
P
DS DSS V
P
Where,IDSSistheshortcircuitdraincurrent,VPisthepinchoffvoltage
SimpleOperationandBreakdownofnChannelJFET

Figure:nChannelFETforvGS=0.
N-Channel JFET Characteristics and Breakdown
BreakDownRegion

Figure:IfvDGexceedsthebreakdownvoltageVB,draincurrentincreasesrapidly.
VDIDCharacteristicsofEMOSFET
Locusofptswhere V DS VGS V P

SaturationorPinch
offReg.

Figure:TypicaldraincharacteristicsofannchannelJFET.
Transfer (Mutual) Characteristics of n-Channel JFET

V
2 IDSS
I I 1 GS
DS DSS V
P

VGS (off)=VP

Figure:Transfer(orMutual)CharacteristicsofnChannelJFET
 JFET Transfer Curve
This graph shows the value of ID for a given
value of VGS
 Biasing Circuits used for JFET

Fixedbiascircuit
Selfbiascircuit
PotentialDividerbiascircuit
JFET(nchannel)BiasingCircuits

ForFixedBiasCircuit
Applying KVL to gate circuit we get

VGG I G RG VGS VGS Fixed ,I G 0

2
V and VGS
2

I I 1 GS
I DS I DSS 1
DS DSS V VP
P and VDS VDD I DS R D
Where, Vp=VGS-off & IDSS is Short ckt. IDS

ForSelfBiasCircuit

VGS I DS RS 0
VGS
I DS
RS
 JFET Biasing Circuits Count
or Fixed Bias Ckt.
 JFET Self (or Source) Bias Circuit

2
V
and I I 1 GS 2
DS DSS V V V V

P I 12 GS GS GS 0
2 DSS V V R
V V P P S
GS
I 1 GS
DSS V R This quadratic equation can be solved for VGS & IDS
P S
 The Potential (Voltage) Divider Bias

2
V V V
I 1 GS G GS 0
DSS V R
P S

Solving this quadratic equation gives V and I

GS DS
A Simple CS Amplifier and Variation in IDS with Vgs
 FET Mid-frequency Analysis:
VDD VDD

A common source (CS) amplifier is shown

RD
to the right. R1
io
The mid-frequency circuit is drawn as follows: D
Co
ii G
the coupling capacitors (Ci and Co) and the +
Rs
+ Ci S
bypass capacitor (CSS) are short circuits +
RL vo
short the DC supply voltage (superposition) vs
vi
R2
_ RSS CSS _
replace the FET with the hybrid- model
_
The resulting mid-frequency circuit is shown below.

io
is ii g d

+ + +
vs RT h vi = v rd RD RL vo
gmv
_ _ _

s mid-frequency CE amplifier circuit s

Analysis of the CS mid-frequency circuit above yields:

vo vo Zi
A vi = = -g m R 'L , where R L' = rd R D R L A vs = = A vi
vi vs R s + Zi
vi i Zi
Zi = = R Th , where R Th = R 1 R 2 A I = o = A vi
ii ii R L
vo po
Zo = = rd R D AP = = A vi A I
io seen by R L
pi
 FET Mid-frequency Analysis:
VDD VDD

A common source (CS) amplifier is shown R1

RD

io
to the right. D
Co
ii
The mid-frequency circuit is drawn as follows: G
Rs +
+ Ci
the coupling capacitors (Ci and Co) and the +
S
RL vo
bypass capacitor (CSS) are short circuits vs vi
R2
CSS _
_ RSS
short the DC supply voltage (superposition) _
replace the FET with the hybrid- model
The resulting mid-frequency circuit is shown below.
io
is ii g d

+ + +
vs RTh vi = v rd RD RL vo
gmv
_ _ _

s mid-frequency CE amplifier circuit s

Analysis of the CS mid-frequency circuit above yields:

vo vo Zi
A vi = = -g m R 'L , where R 'L = rd R D R L A vs = = A vi
vi vs R s + Zi
vi io Z
Zi = = R Th , where R Th = R1 R 2 AI = = A vi i
ii ii R L
vo po
Zo = = rd R D AP = = A vi A I
io seen by R L
pi
Procedure: Analysis of an FET amplifier at mid-frequency:
1) Find the DC Q-point. This will insure that the FET is operating in the saturation
region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
ID 2I
gm = = DSS VGS - VP (for JFET's and DM MOSFET's)
VGS VP2
ID
gm = = K VGS - VT (for EM MOSFET's)
VGS
(Note: Uses DC value of VGS )

3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).
PE-Electrical Review Course - Class 4 (Transistors)
Example 7: 18 V 18 V

500
Find the mid-frequency values for Avi, Avs, AI, AP, Zi, 800 k
io
and Zo for the amplifier shown below. Assume that D
Co
ii G
Ci, Co, and CSS are large. 10 k +
+ Ci S
Note that this is the same biasing circuit used in Ex. + 8k vo
2, so VGS = -0.178 V. vs vi
400 k
CSS _
_ 2k
The JFET has the following specifications: _
DSS = 4 mA, VP = -1.46 V, rd = 50 k
 VDD VDD
FET Amplifier Configurations and
RD
Relationships:
R1
io
D
CS CG CD
Co
ii G
Rs +
' ' g m R 'L
+ + Ci S
RL vo A vi -g m R L gmR L
vs vi
R2 1 g m R 'L
_ RSS C SS _

_ R 'L rd R D R L rd R D R L R SS R L
Common Source (CS) Amplifier 1
Zi R Th R SS R Th
ii S D
io gm
Rs Co
+ Ci
G + 1
+
vi RSS
RD
Zo rd R D rd R D R SS
vs
_
RL vo
gm
R1 _
_ C2 R2 VCC
Zi Zi Z i
A vs A vi A vi A vi
Common Gate (CG) Amplifier
R
s + Z i R s + Zi R s + Zi
Zi Z Zi
VDD VDD
AI A vi A vi i A vi
R1
R L R L RL
D
AP A vi A I A vi A I A vi A I
ii G

+
Rs + Ci S io where R Th = R 1 R 2
vs R2 Co +
vi
_ R SS RL vo Note: The biasing circuit is the same for each amp.
_ _

Common Drain (CD) Amplifier (also called source follower)

Figure:CircuitsymbolforanenhancementmodenchannelMOSFET.
Figure:nChannelEnhancementMOSFETshowingchannellengthLandchannelwidthW.
Figure:ForvGS<Vtothepnjunctionbetweendrainandbodyisreversebiasedandi D=0.
 Figure:ForvGS>Vtoachannelofntypematerialisinducedintheregionunderthegate.
AsvGSincreases,thechannelbecomesthicker.ForsmallvaluesofvDS,iDisproportionaltovDS.
ThedevicebehavesasaresistorwhosevaluedependsonvGS.
Figure:AsvDSincreases,thechannelpinchesdownatthedrainendandiDincreasesmoreslowly.
FinallyforvDS>vGSVto,iDbecomesconstant.
 CurrentVoltageRelationshipof
nEMOSFET

Locusofpointswhere
Figure:Draincharacteristics
Figure:Thiscircuitcanbeusedtoplotdraincharacteristics.
Figure:Diodesprotecttheoxidelayerfromdestructionbystaticelectriccharge.
Figure:SimpleNMOSamplifiercircuitandCharacteristicswithloadline.
Figure:Draincharacteristicsandloadline
FigurevDSversustimeforthecircuitofFigure5.13.
FigureFixedplusselfbiascircuit.
FigureGraphicalsolutionofEquations(5.17)and(5.18).
FigureFixedplusselfbiasedcircuitofExample5.3.
FigureThemorenearlyhorizontalbiaslineresultsinlesschangeintheQpoint.
FigureSmallsignalequivalentcircuitforFETs.
FigureFETsmallsignalequivalentcircuitthataccountsforthedependenceofiDonvDS.
FigureDeterminationofgmandrd.SeeExample5.5.
FigureCommonsourceamplifier.
For drawing an a c equivalent circuit of Amp.
Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model
 AnalysisofCSAmplifier
ACEquivalentCircuit

SimplifiedACEquivalentCircuit

v
Voltage gain, A o
v v
gs
v i R g v R Input imp., Z R R R
o o L m gs L in G 1 2
v
r R
A o g R , R R r Out put imp., Z r R d D
v v m L L D d o d D r R
gs d D
 Analysis of CS Amplifier with Potential Divider Bias

Av gm(rd || RD)

This is a CS amplifier configuration therefore the

input is on the gate and the output is on the drain. Zi R1 || R2

Av gm(rd || RD) Zo rd || RD
Zo RD
rd 10RD
Av gmRD, r 10 R
d D
Figurevo(t)andvin(t)versustimeforthecommonsourceamplifierofFigure5.28.
AnAmplifierCircuitusingMOSFET(CSAmp.)

FigureCommonsourceamplifier.
AsmallsignalequivalentcircuitofCSAmp.

FigureSmallsignalequivalentcircuitforthecommonsourceamplifier.
Figurevo(t)andvin(t)versustimeforthecommonsourceamplifierofFigure5.28.
FigureGainmagnitudeversusfrequencyforthecommonsourceamplifierofFigure5.28.
FigureSourcefollower.
FigureSmallsignalacequivalentcircuitforthesourcefollower.
FigureEquivalentcircuitusedtofindtheoutputresistanceofthesourcefollower.
FigureCommongateamplifier.
FigureSeeExercise5.12.
FigureDraincurrentversusdraintosourcevoltageforzerogatetosourcevoltage.
FigurenChanneldepletionMOSFET.
FigureCharacteristiccurvesforanNMOStransistor.
FigureDraincurrentversusvGSinthesaturationregionfornchanneldevices.
FigurepChannelFETcircuitsymbols.Thesearethesameasthecircuitsymbolsfornchanneldevices,
exceptforthedirectionsofthearrowheads.
FigureDraincurrentversusvGSforseveraltypesofFETs.iDisreferencedintothedrainterminal
fornchanneldevicesandoutofthedrainforpchanneldevices.