Introduction to VLSI

Design

Department of Electronics and Communication Engineering

Under the esteemed guidance of
Mr. Sai Kumar Goud, Professor
Dr.G.Shanmuga Priya, Professor
BY
M Dheeraj Surya Sai 13R01A04E6
Todays Topics

VLSI Overview
Transistor
Structure
Static CMOS Logic

Design Methods & Design Styles

VLSI Trends
Objectives (1/3)
VLSI Circuit Analysis:
Understand MOS transistor operation, design eqns.
Understand simple calculations
Understand static & dynamic CMOS logic
Estimate delay of CMOS gates, networks, & long
wires
Estimate power consumption
Understand design and operation of latches &
flip/flops
Objectives (2/3)
CMOS Processing and Layout
Understand the VLSI manufacturing process.
Have an appreciation of current trends in VLSI
manufacturing.
Understand layout design rules.
Design and analyze layouts for simple digital CMOS
circuits
Design and analyze hierarchical circuit layouts.
Understand ASIC Layout styles.
Objectives (3/3)
VLSI System Design
Understand register-transfer level design.
Design simple combinational and sequential logic
circuits using using a Hardware Description
Language (HDL).
Design small to medium circuits consisting of
multiple components such as a controller and
datapath using a HDL.
Understand the design flows used in industrial IC
design.
Design a small standard-cell chip in its entirety
using a variety of CAD tools and check it for correct
operation.
Roadmap for the term: major
topics
VLSI Overview
CMOS Processing & Fabrication
Components: Transistors, Wires, & Parasitics
Design Rules & Layout
Combinational Circuit Design & Layout
Sequential Circuit Design & Layout
VLSI Overview
Why Make IC
IC Evolution
Common technologies
CMOS Transistors & Logic Gates
Structure

Switch-Level Transistor Model

Basic gates

The VLSI Design Process

Levels of Abstraction

Design steps

Design styles
VLSI Trends
 Why Make ICs
Integration improves
size
speed
power

Integration reduce manufacturing costs

(almost) no manual assembly
 IC Evolution (1/3)
SSI Small Scale Integration (early 1970s)
contained 1 10 logic gates
MSI Medium Scale Integration
logic functions, counters
LSI Large Scale Integration
first microprocessors on the chip
VLSI Very Large Scale Integration
now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2),
floating-point arithmetic unit(s), etc.
 IC Evolution (2/3)
Bipolar technology
TTL (transistor-transistor logic)
ECL (emitter-coupled logic)

MOS (Metal-oxide-silicon)
although invented before bipolar transistor,
was initially difficult to manufacture
nMOS (n-channel MOS) technology developed in
1970s
required fewer masking steps, was denser, and
consumed less power than equivalent bipolar ICs =>
an MOS IC was cheaper than a bipolar IC and led to
investment and growth of the MOS IC market.
IC Evolution (3/3)
CMOS (Complementary MOS): n-channel and p-
channel MOS transistors =>
lower power consumption, simplified fabrication
process
Bi-CMOS - hybrid Bipolar, CMOS (for high
speed)
GaAs - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germanium (for RF)
 Silicon Manufacturing
Alternatives

Standard Components Application Specific ICs

Fixed Application Semi Full Silicon

Application by Programming Custom Custom Compilation

Logic Hardware Software

Families Programming Programming
(MASK)

TTL PLA Microprocessor

CMOS ROM EPROM,EEPROM
PLD
 VLSI Technology - CMOS
Transistors
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected

to V DD

Key feature: p transistor

2002: L=130nm
transistor length L 2003: L=90nm
Polysilicon Gate 2005: L=65nm?
SiO2
Insulator L D D
W
Source Drain
G SB G
n+ n+
channel
p substrate S S
substrate connected
n transistor to GND
Transistor Switch Model
NFET or n transistor L L
on when gate H OFF ON
when gate=H when gate=L
"good" switch for logic L L L
"poor" switch for logic H
"pull-down" device L H

PFET or p transistor
on when gate L OFF ON
when gate=L when gate=H
"good" switch for logic H
H H
"poor" switch for logic L
"pull-up" device H L
CMOS Logic Design
Complementary transistor networks
Pullup: p transistors
Pulldown - n transistors
VDD

VDD
Pullup
Network
(p-transistors)

Inputs Out In Out

Pulldown
Network
(n-transistors)
Gnd

Gnd Inverter
CMOS Inverter Operation

VDD VDD

OFF ON

H L L H

ON OFF

Gnd Gnd
CMOS Logic Example - Whats
This?
A
OUT
B
+VDD
NAND

P Transistors
A B on when gate L

OUT
A
N Transistors
on when gate H
B
A B AND NAND
GND 0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
VLSI Levels of Abstraction
Specification
(what the chip does, inputs/outputs)

Architecture
major resources, connections

Register-Transfer
logic blocks, FSMs, connections

Logic
gates, flip-flops, latches, connections

Circuit
transistors, parasitics, connections

Layout
mask layers, polygons
The VLSI Design Process
Move from higher to lower levels of abstraction
Use CAD tools to automate parts of the process
Use hierarchy to manage complexity
Different design styles trade off:
Design time

Non-recurring engineering (NRE) cost

Unit cost
Performance
Power Consumption
VLSI Design Tradeoffs (1/2)
Non-Recurring Engineering (NRE) Costs
Design Costs
Mask Tooling costs
Unit Cost - related to chip size
Amount of logic

Current technology
Performance
Clock speed
Implementation
VLSI Design Tradeoffs (2/2)
Power consumption - a relatively new concern
Power supply voltage
Clock speed
VLSI Design Styles
FullCustom
Application-Specific Integrated Circuit (ASIC)
Programmable Logic (PLD, FPGA)

System-on-a-Chip
Full Custom Design
Each circuit element carefully handcrafted
Huge design effort
High Design & NRE Costs / Low Unit Cost

High Performance

Typically used for high-volume applications

Application-Specific Integrated
Circuit (ASIC)
Constrained design using pre-designed (and
sometimes pre-manufactured) components
Also called semi-custom design

CAD tools greatly reduce design effort

Low Design Cost / High NRE Cost / Med.

Unit Cost
Medium Performance
Programmable Logic (PLDs,
FPGAs)
Pre-manufactured components with
programmable interconnect
CAD tools greatly reduce design effort

Low Design Cost / Low NRE Cost / High Unit

Cost
Lower Performance
System-on-a-chip (SOC)
Idea: combine several large blocks
Predesigned custom cores (e.g., microcontroller)
- intellectual property (IP)
ASIC logic for special-purpose hardware
Programmable Logic (PLD, FPGA)
Analog

Open issues
Keeping design cost low
Verifying correctness of design
VLSI Trends: Moores Law
In 1965, Gordon Moore predicted that
transistors would continue to shrink, allowing:
Doubled transistor density every 18-24 months
Doubled performance every 18-24 months

History has proven Moore right

But, is the end is in sight?
Physical
limitations
Economic limitations

Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com
Trends in VLSI
Transistor

Smaller, faster, use less power

Interconnect

Less resistive, faster, longer (denser

design)
Yield

Smaller die size, higher yield

Summary - Technology Trends
Processor
Logic capacity increases ~ 30% per year
Clock frequency increases ~ 20% per year
Cost per function decreases ~20% per year
Memory
DRAM capacity: increases ~ 60% per year
(4x every 3 years)
Speed: increases ~ 10% per year
Cost per bit: decreases ~25% per year
 Technology Directions: SIA
Roadmap

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35
Logic trans/cm2 6.2M 18M 39M 84M 180M 390M
Cost/trans (mc) 1.735 .580 .255 .110 .049 .022
#pads/chip 1867 2553 3492 4776 6532 8935
Clock (MHz) 1250 2100 3500 6000 10000 16900
Chip size (mm2) 340 430 520 620 750 900
Wiring levels 6-7 7 7-8 8-9 9 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5
High-perf pow (W) 90 130 160 170 175 183
Scaling
The process of shrinking the layout in which
every dimension is reduced by a factor is
called Scaling.
Transistors become smaller, less resistive,
faster, conducting more electricity and using
less power.
Designs have higher yields and increased
performance.
Can Scaling Continue?
Scaling work well in the past:
Year 1989 1992 1995 1997 1999 2001
Technology
(m) 0.65 0.5 0.35 0.25 0.18 0.15

In
order to keep scaling work in the future,
many technical problems need to be solved.
Can Scaling Continue?
Some characteristics of the transistors do not
scale uniformly, e.g., delay, leakage current,
threshold voltage, etc.
Mismatch in the scaling of transistors and
interconnects. Interconnect delay has
increased from 5-10% of the overall delay to
50-70%.
Complicated Design
Too many transistors and no way to handle
them manually.
Solutions:

CAD

Hierarchical design

Design re-use
Power and Noise
Huge power consumption and heat
dissipation becomes a problem
Noise and cross talk.

Solutions:

Better physical design

Gallery - Early Processors

Mos Technology
6502
Intel 4004
First P - 2300 xtors
L=10m
Gallery - Current Processors

Pentium III PowerPC 7400 (G4)

28M transistors / 733MHz-1Gz / 13-26W 6.5M transistors / 450MHz / 8-10W
L=0.25m shrunk to L=0.18m L=0.15m
Gallery - Current Processors

Pentium 4 Pentium 4 Northwood

42M transistors / 1.3-1.8GHz / 49-55W 55M transistors / 2-2.5GHz
L=0.18m L=0.13m
THANK YOU