Beruflich Dokumente
Kultur Dokumente
Test
VDD
Ron
ic(t)
vi (t) vo(t)
R = large CL
Ground
t=0
i(t) v(t)
V C
dv(t) V -t
i(t) = C = exp( )
dt R RC
V2 -t
Etrans = V i(t) dt = exp( ) dt
0 0 R RC
= CV2
2 V2 -2t
R i (t) dt = R exp( ) dt
0 R 0
2
RC
1
= CV2
2
-t V -t
v(t) i(t) dt = V [1-exp( )] exp( )
dt
0 0 RC R RC
1
= CV2
2
VDD
isc(t)
vi (t) vo(t)
CL
Ground
VTn
p- 0
transistor Iscmaxf
starts
conducting
isc(t)
Isc
Time (ns)
0 tB tE 1
CL tr
tf R = large
vo(t)
Ground
R
-t
VDD[1- exp()]
vo(t) R(t) C
Isc(t) = =
R(t) R(t)
i
Small C Large C
vo(t) vo(t)
iscmax 1
R(t)
t
tf
Copyright Agrawal & Low-Power Design and Test 21
Srivaths, 2007 , Lecture 2
Psc, Rise Times, Capacitance
For given input rise and fall times
short circuit power decreases as
output capacitance increases.
Short circuit power increases with
increase of input rise and fall times.
Short circuit power is reduced if
output rise and fall times are smaller
than the input rise and fall times.
Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit
Static
Leakage
nMOS Transistor
Scaled device
Ic
Log (Drain current)
Isub
Polysilicon
Gate
Drain
Source W
n+ n+
L
p-type body (bulk)
SiO2
Thickness = tox