Lecture 3

Programmable Logic
Devices

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 Silicon Devices

Why HW/SW Co-design?
Hardware (ASIC, FPGA)
Fast
But very expensive
Software (Processor)
Flexible
But slow
Hardware + Software = Good
solution

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 Programmable Logic :
Gate Array
Programmable Logic Device (PLD, PLA,
PAL, ...)
AND-OR combinatorial logic, plus FF
designer writes Boolean equations
Small complexity only
Complex PLD (CPLD)
several PLD blocks
programmable interconnection
matrix

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1. ASIC (Application-specific integrated
circuit)
2. Multi-chip module
3. Computer-on-module
4. SoP (System-on-Package )
5. SoPC (System on a Programmable Chip)
6. SoC (System on Chip)
7. Field Programmable Gate Arrays
(FPGAs)
a. What is a FPGA?
b. Xilinx Field Programmable Gate
Arrays (FPGAs)
c. National Instruments (NI) Field
Programmable Gate Arrays (FPGAs)
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 Digital Design Technologies
Digital
Design
Methodologies

Full Custom IC Semi Custom IC

Standard Gate Field Programmable

Cell Array Logic

Field Programmable Simple/Complex

Digital Design Gate Array PLD
Technologies (FPGA) (S/CPLD)

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 Ease of Use
Full-custom
ICs
* Market Volume to Amortize

Standard
Cells
* Time to Prototype

FPGAs,
Gate Arrays

PLDs

* Nonrecurring engineering cost

* Design Complexity
* Process complexity
* Logic Density Characteristics of
* Speed various
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Digital Design
7
Technologies
 100,000 Gate
No. of Logic Gates / Chip Array/Std.Cell
FPGA ASICs
10,000

1,000

PLD
100

10

10 100 1,000
Design Cycle / Man-Days

Logic Density vs Design Cycle

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 Total Cost
PLDS

Gate Arrays

Fixed
Cost
Breakeven Volume
Qty

Cost Comparison of PLDs and Gate Arrays

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 Discrete Gates and Cell-based and
Standard ICs Full-custom ASICs

cheap unit cost Programmable advanced and specialized

low levels of Logic Devices functionality
integration (FPGAs, CPLDs) high level of integration
standard but limited high performance
functionality tailored for small market
variety of stock segment => inventory
required risk
low performance high non-recurring
engineering cost
high investment cost to
cater for small-volume
requirements

Comparison of Discrete Gates/Standard ICs and

ASICs

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 Programmable Logic Device (PLD) or
Field Programmable Logic Device
(FPLD)
a generic term that refers to any
integrated circuit used for implementing
digital hardware, where the chip can be
configured by the end user to realize
different designs
fixed architecture but functionality
programmable for a specific application

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 PROM PROMs are not classified as
PLDs since they are mainly used
for storage and special-purpose
applications.
PLA, PAL
SPLD

CPLD FPGA

The Evolution of the PLD

Technology

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 Gate Array

1. Each chip is prefabricated with an array
of identical gates or cells.
2. The chip is customized by fabricating
routing layers on top.
3. Time to market, cost

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 3 categories of PLDs:
1. SPLD (Simple Programmable Logic
Device)
PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
Registered PAL
2. CPLD (Complex Programmable Logic
Device)
3. FPGA (Field Programmable Gate Array)

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 Programmable logic array (PLA)

Programmable logic array (PLA)

A programmable logic array (PLA) is a
kind of programmable logic device used to
implement combinational logic circuits. The
PLA has a set of programmable AND gate
planes, which link to a set of programmable
OR gate planes, which can then be
conditionally complemented to produce an
output. This layout allows for a large number
of logic functions to be synthesized in the
sum of products (and sometimes product of
sums) canonical forms

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 PAL
o Programmable AND plane / Fixed OR
plane
o Finite combination of ANDs / ORs
o Medium logic density
o Low fuse count
o Faster than PLAs

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 Inputs

Fixed OR Plane

Outputs
Programmable Programmable Element
AND Plane (e.g. Metallic Fuse, UV EPROM Cell)

The PAL Architecture

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 Inputs

Fixed OR Plane D or T
Flip-flops
Programmable AND Plane

D Q

CLK

D Q

CLK

Clock

The Registered PAL Architecture

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 The features of the PLA were:
Two programmable ground planes
Any combination of ANDs/ORs
Sharing of AND terms across
multiple ORs
Highest logic density available to
user
High fuse count; slower than PALs
Programmable logic array

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PAL (Programmable Array Logic)
The term Programmable Array Logic (PAL)
is used to describe a family of
programmable logic device semiconductors
used to implement logic functions in digital
circuits introduced by Monolithic Memories,
Inc. (MMI) in March 1978.[1] MMI obtained a
registered trademark on the term PAL for use
in "Programmable Semiconductor Logic
Circuits". The trademark is currently held by
Lattice Semiconductor.

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 PAL devices consisted of a small PROM core and
additional output logic used to implement
particular desired logic functions with few
components.
Using specialized machines, PAL devices
were "field-programmable". Each PAL device
was "one-time programmable" (OTP), meaning
that it could not be updated and reused after its
initial programming

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 PLA
o Two programmable planes: AND & OR
planes
o Any combinations of ANDs / ORs
o Sharing of AND terms across multiple
ORs
o High logic density
o High fuse count
o Slower than PALs
o Higher power dissipation than PALs

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 Inputs
Programmable
OR Plane

Programmable
AND Plane

Programmable Element Outputs

(e.g. Metallic Fuse, UV
EPROM Cell)

The PLA Architecture

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 a.CPLD (Complex Programmable Logic Devices)
A complex programmable logic device
(CPLD) is a programmable logic device with
complexity between that of PALs and FPGAs,
and architectural features of both. The building
block of a CPLD is the macrocell, which
contains logic implementing
disjunctive normal form expressions and more
specialized logic operations.

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AComplex Programmable Logic Device
(CPLD)is a combination of a fully programmable
AND/OR array and a bank of macrocells. The
AND/OR array is reprogrammable and can perform
a multitude of logic functions. Macrocells are
functional blocks that perform combinatorial or
sequential logic, and also have the added
flexibility for true or complement, along with
varied feedback paths.
Traditionally, CPLDs have used analog sense
amplifiers to boost the performance of their
architectures.
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 CPLDs feature:
Central global interconnect
Simple, deterministic timing
Easily routed
PLD tools add only interconnect
Wide, fast complex gating
Why Use a CPLD?
Ease of Design:
Lower Development Costs
More Product Revenue:
Reduced Board Area:
Cost of Ownership
Reliability
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 3 basic characteristics distinguish PLDs
from each other :
o architecture of basic functional units
o programmable interconnections
o programming technology

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 Architecture of PLDs
P[0]
in[0] out[0]
nxp P[1] pxm
in[1] out[1]
AND Array : OR Array
: :
:
: (Programmable) (Programmable) :
P[p-1]
in[n-1] out[p-1]

n inputs m outputs
p product terms
fromed from inputs

Generic Architecture of PLDs

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 CPLD
o Each basic logic block is constructed
from registered PLDs
o Central, global interconnects
o Simple and deterministic timing
o Easily routed
o PLD tools add only interconnects
o Wide, fast complex gating
o Clock speed > 300MHz

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 PLD PLD PLD
Programmable
Interconnect

PLD PLD PLD

The CPLD Architecture

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 CPLD Block Structure
I/O

I/O
I/O Block

I/O Block
Block

Block
Interconnection
Interconnection Matrix
Matrix

I/O
I/O Block

Block

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 Clock Product Output
Logic Term Logic
Inputs Outputs
Array Sharing Macrocells
Dedicated Array * Registers
Inputs

Basic PLD Block of a CPLD

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 FPGA
o a regular structure of configurable logic
blocks (or modules) and interconnects
o Channel-based routing
o Fine-grained configurable logic block
o Post-layout timing analysis required
o Tools more complex than CPLDs
o Fast register pipelining

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 Row 1

Horizontal Channel Channel

Row 2
Vertical Channel

Channel
Row 3

I/O Channel
Row 4
Pads

Configurable Logic Blocks Configurable Logic Blocks

(a) Matrix-based Architecture (b) Row-based Architecture
(e.g. Xilinx and QuickLogic devices) (e.g. Actel devices)

The FPGA Architecture

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 Interconnect
Delay
Block
Delay

Size of Logic Block

Both Interconnect Delay and Block Delay
are dependent on the FPGA architecture

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 FPGA
o 2 basic types of FPGAs:
o Reprogrammable (SRAM-based)
o SRAM determines interconnects
o SRAM defines logic in Look Up Table
o OTP (One-time Programmable)
o Interconnect is anti-fuse
o Logic is traditional gates

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 Example:
Show how the PLD shown in Fig 2.1 can be
used to implement typical 2-input logic
functions: AND, OR, NAND, NOR, XOR and
XNOR.

Fig 2.1
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Uses of Programmable Logic
Devices
3 main uses of PLDs:
Replacement of glue logic (random logic)
Implementing dedicated controller circuits
Implementing finite state machines (FSM)

Short Question:
What are the merits of PLDs when
compared with the discrete logic devices
(e.g. TTL 74XX) ?

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 Selection Criteria
Main factors to be considered when
choosing a PLD:
Process technology
Programming technology
reprogrammable vs OTP
UV EPROM, E2EPROM, RAM and Flash
Logic capacity
Dont miss the hidden factor:
utilization
It is a surprise if you can achieve a
utilization well over 70%.
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 Dedicated logic functions
E.g. Flip-flop types, I/O buffers,
macrocells
Timing characteristics & speed
requirements
Tpd, Tsetup, Thold, .
Power dissipation
Voltage requirements
E.g. 2.5V, 3.3V, 5V
I/O pins available
Packages
Special features
E.g. In-system
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 Short Question:
What are the main constraints in PLD-
based design ?

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 PLD Design Flow & Tools
Design Capture
- schematics
- HDL-based file

Functional
Synthesis
SImulation

Timing
Device Fitting
Simulation

Device
In-circuit
Programming/
Testing
Downloading
Typical PLD Design
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44
 PLD Design Flow and Tools
CAD Tools are crucial to implementing
digital circuits in PLDs.
PLD vendors usually offer series of free
or low-cost CAD tools for users.
Examples:
ISE Webpack from Xilinx
MAX Plus from Altera
ispLEVER from Lattice Semiconductor
Warp from Cypress

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 Idea

Schematics HDL State Machine

ECS StateCAD
Design Entry

Synthesis
Xilinx Synthesis Technology (XST)

Translate
NGDBuild

CPLD FPGA

Fitting Mapping
CPLD Fitter MAP/PAR

The Xilinx ISE

Estimation
XPower
Design
Environment
Programming
IMPACT Programmer

TestBench Simulate
HDL ModelSim
Bencher XE

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 Example:
A sequential circuit is implemented into a
PLD as in Fig 2.2.
(a) Identify the architecture of the PLD
device.
i) architectural type
ii) no. of inputs
iii)no. of outputs
iv)maximum number of product terms
available for each output
(b)
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Write a logic equation for each
47
output.
 R'
R R
S'
S S
Q2'
Q2
Q1'
Q1

D Q Q1
CLK
Q

D Q Q2
CLK
Q

D Q Q3
CLK
Q

O4

O5

CLOCK

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