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Digital IC Design

Faculty-in-charge: Dr. Sitangshu Bhattacharya


Department of ECE
Indian Institute of Information Technology-Allahabad
Room No. 2221, CC-I
Telephone: 2131
Email: sitangshu@iiita.ac.in
Digital IC Design

Contents:

o MOS Transistor: Structure, External Bias, o Dynamic Logic Circuits Pass transistors, Voltage
Operation, Current-Voltage Characteristics, Bootstrapping, Synchronous Dynamic Circuit
Capacitances, Small Geometry Scaling Testing, Dynamic CMOS Circuit Techniques, High
performance Dynamic CMOS circuits
o MOS Inverters: Resistive Load Inverter, n-type
MOSFET load inverter, CMOS inverter o Semiconductor Memories DRAM, SRAM, Non-
volatile, Flash Memory, FRAM
o Switching Characteristics and Interconnect
Effects: Delay Time and constraints, Interconnect o Low Power CMOS Logic Circuits Low Power
parasitics, Interconnect delay calculation, Switching Design Switching Activity, Switched Capacitance,
power dissipation of CMOS inverters Adiabatic Logic Circuits

o Combinational MOS Logic Depletion Logic o BiCMOS Logic Circuits BJT, Dynamic behavior,
Circuits with nMOS loads, CMOS logic circuits, BiCMOS static behavior Switching Delay
CMOS transmission gates
o Chip I/O Circuits ESD protection, Output Circuit
o Sequential MOS Logic Bistable elements, SR Noise, On Chip Clock Generation and Distribution,
Latch, Clocked Latch with FF circuits, CMOS D- Latchup and its prevention
latch and Edge Triggered FFs
Reading Materials:
1. CMOS Digital Integrated Circuits Analysis and Design By S-Mo Kang and Y Leblebici
2. Digital Integrated Circuits: Analysis and Design By John E. Ayers
3. Digital Integrated Circuits: A Design Perspective By Anantha P. Chandrakasan,
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017 Borivoje Nikolic, and Jan M. Rabaey
Digital IC Design

Combinational MOS Logic

Combinational MOS Logic


See Kang and Leblebici Book

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

MOS Layout

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

CMOS Layout

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

CMOS NOR2 Layout

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

CMOS NOR2 Layout

CMOS NOR2 Stick Diagram

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

CMOS NAND2 Layout

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram


For any Boolean function, for eg:

The governing lines are:

OR operations parallel connected drivers

AND operations series connected drivers

Inversion nature of MOS ckt. operation

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: For depletion load

OR operations parallel connected drivers

AND operations series connected drivers

Inversion nature of MOS ckt. operation


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: For CMOS

OR operations parallel connected drivers

AND operations series connected drivers

Inversion nature of MOS ckt. operation


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: For CMOS

y A BC
OR operations parallel connected drivers

AND operations series connected drivers

Inversion nature of MOS ckt. operation


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Diffusion Region should be done for parallel connected drivers.

Poly-Si Regions for both pMOS and nMOS: This should be common to all.

Contacts: This must be very less to save power.

Poly Regions Diffusion Regions

Contact Regions

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Visit all the nodes once (but can be repeated).

Edges cant be visited more than once.

The direction of path travelled must be same in both PMOS and NMOS sections.

For multiple solutions in a same problem, all the solutions are identical.

You can start from any node.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
S

D
D S S
S S

D D
D D
D D
D D

S S
D D

S S S S

Choice of direction of path travelled


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
S

D
D S S
S S

D D
D D
D D
D D

S S
D D

S S S S

Then my solution is ABC.


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
S

D
D S S
S S

D D
D D
D D
D D

S S
D D

S S S S

You can take any other directions (must be same in pMOS and NMOS) say : CBA (cyclic rotation)
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
S

D
D S S
S S

D D
D D
D D
D D

S S
D D

S S S S

BAC is not my solution as I cannot return from A to C (Edges must be travelled once).
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
S

D
D S S
S S

D D
D D
D D
D D

S S
D D

S S S S

This actually represents the poly-Si order in the stick diagram for optimization.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S

D D
D D

S
D GND

S S

This actually represents the poly-Si order in the stick diagram for optimization.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S
N-Well

D D
D D

S
D GND

S S

This actually represents the poly-Si order in the stick diagram for optimization.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S
N-Well p-Diff

D D
D D

n-Diff
S
D GND

S S

This actually represents the poly-Si order in the stick diagram for optimization.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D
D D
S D D S S D
A B C
n-Diff
S
D GND

S S

This actually represents the poly-Si order in the stick diagram for optimization.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D GND

S S

Look at the NMOS: Common node of A and B is Vout


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D GND

S S

Look at the NMOS: Common node of C and A is tied to GND.


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D GND

S S

Look at the NMOS: Common node of C and A is tied to GND. What is the problem here?
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D GND

S S

Look at the NMOS: Common node of C and A is tied to GND. What is the problem here?
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017 The two metal lines are short-circuited
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D

S S GND

Look at the NMOS: Common node of C and A is tied to GND. Lower the GND.
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D

S S GND

Look at the pMOS: Common node of B and C is tied to Vout.


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D

S S GND

Look at the pMOS: A is connected to VDD.


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

S
VDD
D
S S A B C
N-Well p-Diff
S D S D DS

D D Vout
D D
S D D S S D
A B C
n-Diff
S
D

S S GND

Look at the pMOS: B and C is connected to A.


Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule


Provides Optimization in Stick/Layout Diagrams

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


CMOS

Vdd = 5V Vdd = 5V

pMOS
Vin Vout Vin Vout
nMOS

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


CMOS
VDD
VDD
X

X
x x x
x X

Gnd Gnd

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


CMOS

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


Depletion Mode
* Note the depletion mode
device

Vdd = 5V

Vout
Vin

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


CMOS

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


NOR-CMOS

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


Examples

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017


Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: Color Coding


Examples

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017